Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

265780916

1

T1

11

T2

1

T3

140

full_word

187194615

1

T1

11

T2

609

T3

140

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	452975241	1			T1	22		T2	610		T3	280
auto[TlIntgErrCmd]	88	1			T69	4		T71	5		T104	8
auto[TlIntgErrData]	112	1			T69	5		T71	9		T104	6
auto[TlIntgErrBoth]	90	1			T69	1		T71	6		T104	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

231639266

1

T1

11

T2

307

T3

268

auto[1]

221336265

1

T1

11

T2

303

T3

12

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	159293910	1			T1	5		T2	1		T3	140
auto[TlIntgErrNone]	partial	auto[1]	106486734	1			T1	6		T54	14		T55	13
auto[TlIntgErrNone]	full_word	auto[0]	72345217	1			T1	6		T2	306		T3	128
auto[TlIntgErrNone]	full_word	auto[1]	114849380	1			T1	5		T2	303		T3	12
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T69	2		T71	5		T104	4
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T69	2		T104	4		T105	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T151	1		T153	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T152	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	55	1			T69	3		T71	3		T104	3
auto[TlIntgErrData]	partial	auto[1]	45	1			T69	2		T71	4		T104	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T71	2		T106	1		T154	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T104	1		T121	1		T155	2
auto[TlIntgErrBoth]	partial	auto[0]	32	1			T71	2		T104	3		T105	3
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T69	1		T71	3		T104	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T156	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T71	1		T153	1		-	-