Unified Coverage Report :: Module :: sha3pad

Module : sha3pad

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.89	99.41	88.37		80.95	95.70	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_pad	95.59	99.41	88.37		94.44	95.70	100.00

---

Module Instance : tb.dut.u_sha3.u_pad

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.59	99.41	88.37		94.44	95.70	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.34	99.45	88.37	100.00	94.44	95.79	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.09	97.30	81.25		100.00	91.89	100.00	u_sha3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prefix_slicer	100.00	100.00					100.00
u_sentmsg_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : sha3pad

	Line No.	Total	Covered	Percent
TOTAL		170	169	99.41
ALWAYS	157	6	6	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	241	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
ALWAYS	266	6	6	100.00
ALWAYS	278	3	3	100.00
CONT_ASSIGN	285	1	1	100.00
ALWAYS	292	3	3	100.00
ALWAYS	297	76	75	98.68
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	519	1	1	100.00
CONT_ASSIGN	537	1	1	100.00
ALWAYS	557	4	4	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
ALWAYS	590	5	5	100.00
ALWAYS	602	5	5	100.00
ALWAYS	614	5	5	100.00
ALWAYS	663	10	10	100.00
ALWAYS	679	17	17	100.00
ALWAYS	778	6	6	100.00
ALWAYS	787	6	6	100.00
ALWAYS	797	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
208	1	1
212	1	1
235	1	1
241	1	1
246	1	1
256	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
271	1	1
			MISSING_ELSE
278	3	3
285	1	1
292	2	2
293	1	1
297	1	1
300	1	1
301	1	1
303	1	1
305	1	1
306	1	1
308	1	1
309	1	1
311	1	1
313	1	1
315	1	1
324	1	1
326	1	1
327	1	1
329	1	1
332	1	1
344	1	1
346	1	1
347	1	1
349	1	1
350	1	1
351	1	1
353	1	1
355	1	1
360	1	1
362	1	1
363	1	1
365	1	1
374	1	1
376	1	1
377	1	1
379	1	1
380	1	1
382	1	1
384	1	1
385	1	1
386	1	1
387	1	1
388	1	1
391	1	1
393	1	1
399	1	1
401	1	1
402	1	1
404	1	1
413	1	1
415	1	1
417	1	1
420	1	1
423	1	1
424	1	1
425	1	1
426	1	1
427	1	1
429	0	1
434	1	1
436	1	1
437	1	1
446	1	1
450	1	1
451	1	1
453	1	1
454	1	1
455	1	1
457	1	1
459	1	1
465	1	1
466	1	1
468	1	1
469	1	1
471	1	1
473	1	1
479	1	1
480	1	1
493	1	1
494	1	1
			MISSING_ELSE
508	1	1
519	1	1
537	1	1
557	1	1
558	1	1
559	1	1
560	1	1
577	1	1
587	1	1
590	1	1
591	1	1
592	1	1
593	1	1
594	1	1
602	1	1
603	1	1
604	1	1
605	1	1
606	1	1
614	1	1
615	1	1
616	1	1
617	1	1
618	1	1
663	1	1
664	1	1
665	1	1
666	1	1
667	1	1
668	1	1
670	1	1
671	1	1
672	1	1
673	1	1
			MISSING_ELSE
679	1	1
681	1	1
682	1	1
685	1	1
686	1	1
689	1	1
690	1	1
693	1	1
694	1	1
697	1	1
698	1	1
701	1	1
702	1	1
705	1	1
706	1	1
709	1	1
710	1	1
778	1	1
779	1	1
780	1	1
781	1	1
782	1	1
783	1	1
			MISSING_ELSE
787	1	1
788	1	1
789	1	1
790	1	1
791	1	1
792	1	1
			MISSING_ELSE
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
			MISSING_ELSE

---

Cond Coverage for Module : sha3pad

	Total	Covered	Percent
Conditions	43	38	88.37
Logical	43	38	88.37
Non-Logical	0	0
Event	0	0

 LINE       208
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T11

 LINE       212
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       235
 EXPRESSION ((mode_i == CShake) ? 1'b1 : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T11,T28

 LINE       235
 SUB-EXPRESSION (mode_i == CShake)
                ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T11,T28

 LINE       241
 EXPRESSION ((sent_message == block_addr_limit) ? 1'b1 : 1'b0)
             -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T11

 LINE       241
 SUB-EXPRESSION (sent_message == block_addr_limit)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T11

 LINE       246
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T11

 LINE       256
 EXPRESSION ((&msg_strb_i) != 1'b1)
            -----------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       285
 EXPRESSION (((sent_message + 1'b1) == block_addr_limit) ? 1'b1 : 1'b0)
             ---------------------1---------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T11

 LINE       285
 SUB-EXPRESSION ((sent_message + 1'b1) == block_addr_limit)
                ---------------------1---------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T11

 LINE       376
 EXPRESSION (msg_valid_i && msg_partial)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T9
1	0	Covered	T4,T5,T9
1	1	Covered	T4,T5,T9

 LINE       387
 EXPRESSION (process_latched || process_i)
             -------1-------    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T9
0	1	Covered	T4,T5,T9
1	0	Covered	T4,T5,T10

 LINE       417
 EXPRESSION (keccak_ack && end_of_block)
             -----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T9
1	1	Covered	T4,T5,T9

 LINE       587
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       603
 EXPRESSION (msg_valid_i & ((~hold_msg)) & ((~en_msgbuf)))
             -----1-----   ------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T9
1	0	1	Covered	T13,T33,T48
1	1	0	Covered	T4,T5,T9
1	1	1	Covered	T4,T5,T9

 LINE       615
 EXPRESSION (en_msgbuf | (keccak_ready_i & ((~hold_msg))))
             ----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T9
0	1	Covered	T4,T5,T9
1	0	Not Covered

 LINE       615
 SUB-EXPRESSION (keccak_ready_i & ((~hold_msg)))
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T9
1	1	Covered	T4,T5,T9

---

FSM Coverage for Module : sha3pad

Summary for FSM :: st

	Total	Covered	Percent
States	10	10	100.00	(Not included in score)
Transitions	21	17	80.95
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StMessage	329	Covered	T1
StMessageWait	382	Covered	T1
StPad	388	Covered	T1
StPad01	426	Covered	T1
StPadFlush	434	Covered	T1
StPadIdle	332	Covered	T1
StPadRun	420	Covered	T1
StPrefix	327	Covered	T1
StPrefixWait	347	Covered	T1
StTerminalError	494	Covered	T1

transitions	Line No.	Covered	Tests
StMessage->StMessageWait	382	Covered	T1
StMessage->StPad	388	Covered	T1
StMessage->StTerminalError	494	Covered	T1
StMessageWait->StMessage	402	Covered	T1
StMessageWait->StTerminalError	494	Covered	T1
StPad->StPad01	426	Covered	T1
StPad->StPadRun	420	Covered	T1
StPad->StTerminalError	494	Not Covered
StPad01->StPadFlush	451	Covered	T1
StPad01->StTerminalError	494	Not Covered
StPadFlush->StPadIdle	469	Covered	T1
StPadFlush->StTerminalError	494	Not Covered
StPadIdle->StMessage	329	Covered	T1
StPadIdle->StPrefix	327	Covered	T1
StPadIdle->StTerminalError	494	Covered	T1
StPadRun->StPadFlush	434	Covered	T1
StPadRun->StTerminalError	494	Not Covered
StPrefix->StPrefixWait	347	Covered	T1
StPrefix->StTerminalError	494	Covered	T1
StPrefixWait->StMessage	363	Covered	T1
StPrefixWait->StTerminalError	494	Covered	T1

---

Branch Coverage for Module : sha3pad

	Line No.	Total	Covered	Percent
Branches		93	89	95.70
TERNARY	212	2	2	100.00
TERNARY	235	2	2	100.00
TERNARY	241	2	2	100.00
TERNARY	285	2	2	100.00
TERNARY	587	2	2	100.00
CASE	157	6	5	83.33
IF	266	4	4	100.00
IF	278	2	2	100.00
IF	292	2	2	100.00
CASE	315	23	22	95.65
IF	493	2	2	100.00
CASE	557	4	3	75.00
CASE	590	5	5	100.00
CASE	602	5	5	100.00
CASE	614	5	5	100.00
IF	663	4	4	100.00
IF	778	4	4	100.00
IF	787	4	4	100.00
IF	797	4	4	100.00
CASE	679	9	8	88.89

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	212	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	235	((mode_i == CShake)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T28
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	241	((sent_message == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	285	(((sent_message + 1'b1) == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	587	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	157	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T4,T5,T6
L224	Covered	T13,T15,T53
L256	Covered	T4,T5,T6
L384	Covered	T5,T9,T31
L512	Covered	T4,T29,T13
default	Not Covered

	LineNo.	Expression
-1-:	266	if ((!rst_ni))
-2-:	268	if (process_i)
-3-:	270	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T9
0	0	1	Covered	T4,T5,T9
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	278	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	292	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	315	case (st)
-2-:	324	if (start_i)
-3-:	326	if (mode_eq_cshake)
-4-:	346	if (sent_blocksize)
-5-:	362	if (keccak_complete_i)
-6-:	376	if ((msg_valid_i && msg_partial))
-7-:	380	if (sent_blocksize)
-8-:	387	if ((process_latched || process_i))
-9-:	401	if (keccak_complete_i)
-10-:	417	if ((keccak_ack && end_of_block))
-11-:	425	if (keccak_ack)
-12-:	450	if (sent_blocksize)
-13-:	468	if (keccak_complete_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StPadIdle	1	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T9
StPadIdle	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T9
StPadIdle	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPrefix	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T9
StPrefix	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T9
StPrefixWait	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
StPrefixWait	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T4,T11,T9
StMessage	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T4,T5,T9
StMessage	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T4,T5,T9
StMessage	-	-	-	-	0	0	1	-	-	-	-	-	Covered	T4,T5,T9
StMessage	-	-	-	-	0	0	0	-	-	-	-	-	Covered	T4,T5,T9
StMessageWait	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T4,T5,T9
StMessageWait	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T4,T5,T9
StPad	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T4,T5,T9
StPad	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T4,T5,T9
StPad	-	-	-	-	-	-	-	-	0	0	-	-	Not Covered
StPadRun	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T9
StPad01	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T4,T5,T9
StPad01	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T4,T5,T9
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T5,T9
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T5,T9
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	493	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T6,T11,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	557	case (mode_i)

Branches:

-1-	Status	Tests
Sha3	Covered	T4,T5,T6
Shake	Covered	T4,T28,T9
CShake	Covered	T4,T11,T28
default	Not Covered

	LineNo.	Expression
-1-:	590	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T4,T5,T9
MuxPrefix	Covered	T4,T11,T9
MuxFuncPad	Covered	T4,T5,T9
MuxZeroEnd	Covered	T4,T5,T9
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	602	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T4,T5,T9
MuxPrefix	Covered	T4,T11,T9
MuxFuncPad	Covered	T4,T5,T9
MuxZeroEnd	Covered	T4,T5,T9
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	614	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T4,T5,T9
MuxPrefix	Covered	T4,T11,T9
MuxFuncPad	Covered	T4,T5,T9
MuxZeroEnd	Covered	T4,T5,T9
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	663	if ((!rst_ni))
-2-:	666	if (en_msgbuf)
-3-:	671	if (clr_msgbuf)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T9
0	0	1	Covered	T4,T5,T9
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	778	if ((!rst_ni))
-2-:	780	if (start_i)
-3-:	782	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T11
0	0	1	Covered	T4,T5,T9
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	787	if ((!rst_ni))
-2-:	789	if (start_i)
-3-:	791	if (process_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T11
0	0	1	Covered	T4,T5,T9
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	797	if ((!rst_ni))
-2-:	799	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_o))
-3-:	801	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T9
0	0	1	Covered	T4,T5,T9
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	679	case (msg_strb)

Branches:

-1-	Status	Tests
7'b0000000	Covered	T4,T5,T6
7'b0000001	Covered	T4,T5,T9
7'b0000011	Covered	T4,T5,T9
7'b0000111	Covered	T4,T5,T9
7'b0001111	Covered	T4,T5,T9
7'b0011111	Covered	T4,T5,T9
7'b0111111	Covered	T4,T5,T9
7'b1111111	Covered	T4,T5,T9
default	Not Covered

---

Assert Coverage for Module : sha3pad

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	4	4	100.00	4	100.00
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AbsorbedPulse_A	2147483647	345696	0	0
AlwaysPartialMsgBuf_M	2147483647	197764	0	0
CompleteBlockWhenProcess_A	2147483647	333571	0	0
DoneCondition_M	2147483647	345679	0	0
DonePulse_A	2147483647	345679	0	0
KeccakAddrInRange_A	2147483647	53010624	0	0
KeccakRunPulse_A	2147483647	3073126	0	0
MessageCondition_M	2147483647	48277822	0	0
ModeStableDuringOp_M	2147483647	35401	0	0
MsgReadyCondition_A	2147483647	2132388043	0	0
MsgWidthidth_A	1048	1048	0	0
NoPartialMsgFifo_M	2147483647	48080058	0	0
Pad01NotAttheEndOfBlock_A	2147483647	335022	0	0
PartialEndOfMsg_M	2147483647	197764	0	0
PrefixLessThanBlock_A	1048	1048	0	0
ProcessCondition_M	2147483647	345698	0	0
ProcessPulse_A	2147483647	345698	0	0
StartCondition_M	2147483647	345816	0	0
StartProcessDoneMutex_a	2147483647	2147483647	0	0
StartPulse_A	2147483647	345816	0	0
StrengthStableDuringOp_M	2147483647	42345	0	0
u_state_regs_A	2147483647	2147483647	0	0

AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345696	0	0
T4	433149	97	0	0
T5	150232	310	0	0
T6	365006	0	0	0
T9	159318	45	0	0
T10	250375	177	0	0
T11	4277	0	0	0
T13	0	173	0	0
T23	0	9	0	0
T28	69577	0	0	0
T29	17129	9	0	0
T30	26458	9	0	0
T31	475078	310	0	0
T38	0	2337	0	0

AlwaysPartialMsgBuf_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	197764	0	0
T4	433149	83	0	0
T5	150232	270	0	0
T6	365006	0	0	0
T9	159318	41	0	0
T10	250375	150	0	0
T11	4277	0	0	0
T13	0	158	0	0
T23	0	9	0	0
T28	69577	0	0	0
T29	17129	8	0	0
T30	26458	9	0	0
T31	475078	270	0	0
T38	0	1058	0	0

CompleteBlockWhenProcess_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	333571	0	0
T4	433149	95	0	0
T5	150232	287	0	0
T6	365006	0	0	0
T9	159318	41	0	0
T10	250375	164	0	0
T11	4277	0	0	0
T13	0	170	0	0
T23	0	9	0	0
T28	69577	0	0	0
T29	17129	9	0	0
T30	26458	9	0	0
T31	475078	287	0	0
T38	0	2283	0	0

DoneCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345679	0	0
T4	433149	97	0	0
T5	150232	310	0	0
T6	365006	0	0	0
T9	159318	45	0	0
T10	250375	177	0	0
T11	4277	0	0	0
T13	0	173	0	0
T23	0	9	0	0
T28	69577	0	0	0
T29	17129	9	0	0
T30	26458	9	0	0
T31	475078	310	0	0
T38	0	2337	0	0

DonePulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345679	0	0
T4	433149	97	0	0
T5	150232	310	0	0
T6	365006	0	0	0
T9	159318	45	0	0
T10	250375	177	0	0
T11	4277	0	0	0
T13	0	173	0	0
T23	0	9	0	0
T28	69577	0	0	0
T29	17129	9	0	0
T30	26458	9	0	0
T31	475078	310	0	0
T38	0	2337	0	0

KeccakAddrInRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	53010624	0	0
T4	433149	67471	0	0
T5	150232	71006	0	0
T6	365006	0	0	0
T9	159318	7663	0	0
T10	250375	120275	0	0
T11	4277	17	0	0
T13	0	31193	0	0
T28	69577	0	0	0
T29	17129	385	0	0
T30	26458	607	0	0
T31	475078	71006	0	0
T38	0	276087	0	0

KeccakRunPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3073126	0	0
T4	433149	3615	0	0
T5	150232	5462	0	0
T6	365006	0	0	0
T9	159318	395	0	0
T10	250375	6391	0	0
T11	4277	1	0	0
T13	0	1675	0	0
T28	69577	0	0	0
T29	17129	21	0	0
T30	26458	31	0	0
T31	475078	5462	0	0
T38	0	13147	0	0

MessageCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48277822	0	0
T4	433149	64930	0	0
T5	150232	69082	0	0
T6	365006	0	0	0
T9	159318	6387	0	0
T10	250375	116144	0	0
T11	4277	0	0	0
T13	0	26216	0	0
T23	0	286	0	0
T28	69577	0	0	0
T29	17129	133	0	0
T30	26458	286	0	0
T31	475078	69082	0	0
T38	0	241576	0	0

ModeStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35401	0	0
T4	433149	31	0	0
T5	150232	0	0	0
T6	365006	0	0	0
T9	159318	20	0	0
T10	250375	68	0	0
T11	4277	1	0	0
T13	0	80	0	0
T23	0	1	0	0
T28	69577	31	0	0
T29	17129	5	0	0
T30	26458	1	0	0
T31	475078	0	0	0
T38	0	1	0	0

MsgReadyCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2132388043	0	0
T4	433149	361965	0	0
T5	150232	766401	0	0
T6	365006	0	0	0
T9	159318	702535	0	0
T10	250375	120166	0	0
T11	4277	0	0	0
T13	0	767432	0	0
T23	0	8355	0	0
T28	69577	0	0	0
T29	17129	1120	0	0
T30	26458	9228	0	0
T31	475078	397460	0	0
T38	0	341707	0	0

MsgWidthidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1048	1048	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0

NoPartialMsgFifo_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48080058	0	0
T4	433149	64847	0	0
T5	150232	68812	0	0
T6	365006	0	0	0
T9	159318	6346	0	0
T10	250375	115994	0	0
T11	4277	0	0	0
T13	0	26058	0	0
T23	0	277	0	0
T28	69577	0	0	0
T29	17129	125	0	0
T30	26458	277	0	0
T31	475078	68812	0	0
T38	0	240518	0	0

Pad01NotAttheEndOfBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	335022	0	0
T4	433149	96	0	0
T5	150232	289	0	0
T6	365006	0	0	0
T9	159318	41	0	0
T10	250375	167	0	0
T11	4277	0	0	0
T13	0	171	0	0
T23	0	9	0	0
T28	69577	0	0	0
T29	17129	9	0	0
T30	26458	9	0	0
T31	475078	289	0	0
T38	0	2289	0	0

PartialEndOfMsg_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	197764	0	0
T4	433149	83	0	0
T5	150232	270	0	0
T6	365006	0	0	0
T9	159318	41	0	0
T10	250375	150	0	0
T11	4277	0	0	0
T13	0	158	0	0
T23	0	9	0	0
T28	69577	0	0	0
T29	17129	8	0	0
T30	26458	9	0	0
T31	475078	270	0	0
T38	0	1058	0	0

PrefixLessThanBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1048	1048	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0

ProcessCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345698	0	0
T4	433149	97	0	0
T5	150232	310	0	0
T6	365006	0	0	0
T9	159318	45	0	0
T10	250375	177	0	0
T11	4277	0	0	0
T13	0	173	0	0
T23	0	9	0	0
T28	69577	0	0	0
T29	17129	9	0	0
T30	26458	9	0	0
T31	475078	310	0	0
T38	0	2337	0	0

ProcessPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345698	0	0
T4	433149	97	0	0
T5	150232	310	0	0
T6	365006	0	0	0
T9	159318	45	0	0
T10	250375	177	0	0
T11	4277	0	0	0
T13	0	173	0	0
T23	0	9	0	0
T28	69577	0	0	0
T29	17129	9	0	0
T30	26458	9	0	0
T31	475078	310	0	0
T38	0	2337	0	0

StartCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345816	0	0
T4	433149	97	0	0
T5	150232	310	0	0
T6	365006	0	0	0
T9	159318	47	0	0
T10	250375	177	0	0
T11	4277	1	0	0
T13	0	177	0	0
T28	69577	0	0	0
T29	17129	9	0	0
T30	26458	9	0	0
T31	475078	310	0	0
T38	0	2337	0	0

StartProcessDoneMutex_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	433149	433143	0	0
T5	150232	150225	0	0
T6	365006	351920	0	0
T9	159318	159306	0	0
T10	250375	250366	0	0
T11	4277	4100	0	0
T28	69577	69519	0	0
T29	17129	17072	0	0
T30	26458	26399	0	0
T31	475078	475073	0	0

StartPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345816	0	0
T4	433149	97	0	0
T5	150232	310	0	0
T6	365006	0	0	0
T9	159318	47	0	0
T10	250375	177	0	0
T11	4277	1	0	0
T13	0	177	0	0
T28	69577	0	0	0
T29	17129	9	0	0
T30	26458	9	0	0
T31	475078	310	0	0
T38	0	2337	0	0

StrengthStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	42345	0	0
T4	433149	54	0	0
T5	150232	2	0	0
T6	365006	171	0	0
T9	159318	31	0	0
T10	250375	90	0	0
T11	4277	3	0	0
T28	69577	25	0	0
T29	17129	6	0	0
T30	26458	2	0	0
T31	475078	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	433149	433143	0	0
T5	150232	150225	0	0
T6	365006	351920	0	0
T9	159318	159306	0	0
T10	250375	250366	0	0
T11	4277	4100	0	0
T28	69577	69519	0	0
T29	17129	17072	0	0
T30	26458	26399	0	0
T31	475078	475073	0	0

---

Cover Directives for Properties: Details

Name	Attempts	Matches	Incomplete
StComplete_C	2147483647	33566900	0
StMessageFeed_C	2147483647	2135421830	0
StPadSendMsg_C	2147483647	3843417	0
StPad_C	2147483647	335021	0

StComplete_C

Name	Attempts	Matches	Incomplete
Total	2147483647	33566900	0
T4	433149	9409	0
T5	150232	30070	0
T6	365006	0	0
T9	159318	4365	0
T10	250375	17169	0
T11	4277	0	0
T13	0	16781	0
T23	0	873	0
T28	69577	0	0
T29	17129	873	0
T30	26458	873	0
T31	475078	30070	0
T38	0	226689	0

StMessageFeed_C

Name	Attempts	Matches	Incomplete
Total	2147483647	2135421830	0
T4	433149	362318	0
T5	150232	771863	0
T6	365006	0	0
T9	159318	702890	0
T10	250375	120792	0
T11	4277	0	0
T13	0	768962	0
T23	0	8377	0
T28	69577	0	0
T29	17129	1135	0
T30	26458	9250	0
T31	475078	398006	0
T38	0	343022	0

StPadSendMsg_C

Name	Attempts	Matches	Incomplete
Total	2147483647	3843417	0
T4	433149	974	0
T5	150232	1884	0
T6	365006	0	0
T9	159318	508	0
T10	250375	1642	0
T11	4277	0	0
T13	0	2221	0
T23	0	144	0
T28	69577	0	0
T29	17129	137	0
T30	26458	144	0
T31	475078	1884	0
T38	0	33232	0

StPad_C

Name	Attempts	Matches	Incomplete
Total	2147483647	335021	0
T4	433149	96	0
T5	150232	289	0
T6	365006	0	0
T9	159318	41	0
T10	250375	167	0
T11	4277	0	0
T13	0	171	0
T23	0	9	0
T28	69577	0	0
T29	17129	9	0
T30	26458	9	0
T31	475078	289	0
T38	0	2289	0

Line Coverage for Instance : tb.dut.u_sha3.u_pad

	Line No.	Total	Covered	Percent
TOTAL		170	169	99.41
ALWAYS	157	6	6	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	241	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
ALWAYS	266	6	6	100.00
ALWAYS	278	3	3	100.00
CONT_ASSIGN	285	1	1	100.00
ALWAYS	292	3	3	100.00
ALWAYS	297	76	75	98.68
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	519	1	1	100.00
CONT_ASSIGN	537	1	1	100.00
ALWAYS	557	4	4	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
ALWAYS	590	5	5	100.00
ALWAYS	602	5	5	100.00
ALWAYS	614	5	5	100.00
ALWAYS	663	10	10	100.00
ALWAYS	679	17	17	100.00
ALWAYS	778	6	6	100.00
ALWAYS	787	6	6	100.00
ALWAYS	797	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
208	1	1
212	1	1
235	1	1
241	1	1
246	1	1
256	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
271	1	1
			MISSING_ELSE
278	3	3
285	1	1
292	2	2
293	1	1
297	1	1
300	1	1
301	1	1
303	1	1
305	1	1
306	1	1
308	1	1
309	1	1
311	1	1
313	1	1
315	1	1
324	1	1
326	1	1
327	1	1
329	1	1
332	1	1
344	1	1
346	1	1
347	1	1
349	1	1
350	1	1
351	1	1
353	1	1
355	1	1
360	1	1
362	1	1
363	1	1
365	1	1
374	1	1
376	1	1
377	1	1
379	1	1
380	1	1
382	1	1
384	1	1
385	1	1
386	1	1
387	1	1
388	1	1
391	1	1
393	1	1
399	1	1
401	1	1
402	1	1
404	1	1
413	1	1
415	1	1
417	1	1
420	1	1
423	1	1
424	1	1
425	1	1
426	1	1
427	1	1
429	0	1
434	1	1
436	1	1
437	1	1
446	1	1
450	1	1
451	1	1
453	1	1
454	1	1
455	1	1
457	1	1
459	1	1
465	1	1
466	1	1
468	1	1
469	1	1
471	1	1
473	1	1
479	1	1
480	1	1
493	1	1
494	1	1
			MISSING_ELSE
508	1	1
519	1	1
537	1	1
557	1	1
558	1	1
559	1	1
560	1	1
577	1	1
587	1	1
590	1	1
591	1	1
592	1	1
593	1	1
594	1	1
602	1	1
603	1	1
604	1	1
605	1	1
606	1	1
614	1	1
615	1	1
616	1	1
617	1	1
618	1	1
663	1	1
664	1	1
665	1	1
666	1	1
667	1	1
668	1	1
670	1	1
671	1	1
672	1	1
673	1	1
			MISSING_ELSE
679	1	1
681	1	1
682	1	1
685	1	1
686	1	1
689	1	1
690	1	1
693	1	1
694	1	1
697	1	1
698	1	1
701	1	1
702	1	1
705	1	1
706	1	1
709	1	1
710	1	1
778	1	1
779	1	1
780	1	1
781	1	1
782	1	1
783	1	1
			MISSING_ELSE
787	1	1
788	1	1
789	1	1
790	1	1
791	1	1
792	1	1
			MISSING_ELSE
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sha3.u_pad

	Total	Covered	Percent
Conditions	43	38	88.37
Logical	43	38	88.37
Non-Logical	0	0
Event	0	0

 LINE       208
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T11

 LINE       212
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       235
 EXPRESSION ((mode_i == CShake) ? 1'b1 : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T11,T28

 LINE       235
 SUB-EXPRESSION (mode_i == CShake)
                ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T11,T28

 LINE       241
 EXPRESSION ((sent_message == block_addr_limit) ? 1'b1 : 1'b0)
             -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T11

 LINE       241
 SUB-EXPRESSION (sent_message == block_addr_limit)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T11

 LINE       246
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T11

 LINE       256
 EXPRESSION ((&msg_strb_i) != 1'b1)
            -----------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       285
 EXPRESSION (((sent_message + 1'b1) == block_addr_limit) ? 1'b1 : 1'b0)
             ---------------------1---------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T11

 LINE       285
 SUB-EXPRESSION ((sent_message + 1'b1) == block_addr_limit)
                ---------------------1---------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T11

 LINE       376
 EXPRESSION (msg_valid_i && msg_partial)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T9
1	0	Covered	T4,T5,T9
1	1	Covered	T4,T5,T9

 LINE       387
 EXPRESSION (process_latched || process_i)
             -------1-------    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T9
0	1	Covered	T4,T5,T9
1	0	Covered	T4,T5,T10

 LINE       417
 EXPRESSION (keccak_ack && end_of_block)
             -----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T9
1	1	Covered	T4,T5,T9

 LINE       587
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       603
 EXPRESSION (msg_valid_i & ((~hold_msg)) & ((~en_msgbuf)))
             -----1-----   ------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T9
1	0	1	Covered	T13,T33,T48
1	1	0	Covered	T4,T5,T9
1	1	1	Covered	T4,T5,T9

 LINE       615
 EXPRESSION (en_msgbuf | (keccak_ready_i & ((~hold_msg))))
             ----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T9
0	1	Covered	T4,T5,T9
1	0	Not Covered

 LINE       615
 SUB-EXPRESSION (keccak_ready_i & ((~hold_msg)))
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T9
1	1	Covered	T4,T5,T9

---

FSM Coverage for Instance : tb.dut.u_sha3.u_pad

Summary for FSM :: st

	Total	Covered	Percent
States	10	10	100.00	(Not included in score)
Transitions	18	17	94.44
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StMessage	329	Covered	T1
StMessageWait	382	Covered	T1
StPad	388	Covered	T1
StPad01	426	Covered	T1
StPadFlush	434	Covered	T1
StPadIdle	332	Covered	T1
StPadRun	420	Covered	T1
StPrefix	327	Covered	T1
StPrefixWait	347	Covered	T1
StTerminalError	494	Covered	T1

transitions	Line No.	Covered	Tests	Exclude Annotation
StMessage->StMessageWait	382	Covered	T1
StMessage->StPad	388	Covered	T1
StMessage->StTerminalError	494	Covered	T1
StMessageWait->StMessage	402	Covered	T1
StMessageWait->StTerminalError	494	Covered	T1
StPad->StPad01	426	Covered	T1
StPad->StPadRun	420	Covered	T1
StPad->StTerminalError	494	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPad01->StPadFlush	451	Covered	T1
StPad01->StTerminalError	494	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPadFlush->StPadIdle	469	Covered	T1
StPadFlush->StTerminalError	494	Not Covered
StPadIdle->StMessage	329	Covered	T1
StPadIdle->StPrefix	327	Covered	T1
StPadIdle->StTerminalError	494	Covered	T1
StPadRun->StPadFlush	434	Covered	T1
StPadRun->StTerminalError	494	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPrefix->StPrefixWait	347	Covered	T1
StPrefix->StTerminalError	494	Covered	T1
StPrefixWait->StMessage	363	Covered	T1
StPrefixWait->StTerminalError	494	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sha3.u_pad

	Line No.	Total	Covered	Percent
Branches		93	89	95.70
TERNARY	212	2	2	100.00
TERNARY	235	2	2	100.00
TERNARY	241	2	2	100.00
TERNARY	285	2	2	100.00
TERNARY	587	2	2	100.00
CASE	157	6	5	83.33
IF	266	4	4	100.00
IF	278	2	2	100.00
IF	292	2	2	100.00
CASE	315	23	22	95.65
IF	493	2	2	100.00
CASE	557	4	3	75.00
CASE	590	5	5	100.00
CASE	602	5	5	100.00
CASE	614	5	5	100.00
IF	663	4	4	100.00
IF	778	4	4	100.00
IF	787	4	4	100.00
IF	797	4	4	100.00
CASE	679	9	8	88.89

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	212	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	235	((mode_i == CShake)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T28
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	241	((sent_message == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	285	(((sent_message + 1'b1) == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	587	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	157	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T4,T5,T6
L224	Covered	T13,T15,T53
L256	Covered	T4,T5,T6
L384	Covered	T5,T9,T31
L512	Covered	T4,T29,T13
default	Not Covered

	LineNo.	Expression
-1-:	266	if ((!rst_ni))
-2-:	268	if (process_i)
-3-:	270	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T9
0	0	1	Covered	T4,T5,T9
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	278	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	292	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	315	case (st)
-2-:	324	if (start_i)
-3-:	326	if (mode_eq_cshake)
-4-:	346	if (sent_blocksize)
-5-:	362	if (keccak_complete_i)
-6-:	376	if ((msg_valid_i && msg_partial))
-7-:	380	if (sent_blocksize)
-8-:	387	if ((process_latched || process_i))
-9-:	401	if (keccak_complete_i)
-10-:	417	if ((keccak_ack && end_of_block))
-11-:	425	if (keccak_ack)
-12-:	450	if (sent_blocksize)
-13-:	468	if (keccak_complete_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StPadIdle	1	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T9
StPadIdle	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T9
StPadIdle	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPrefix	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T9
StPrefix	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T9
StPrefixWait	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T9,T10
StPrefixWait	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T4,T11,T9
StMessage	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T4,T5,T9
StMessage	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T4,T5,T9
StMessage	-	-	-	-	0	0	1	-	-	-	-	-	Covered	T4,T5,T9
StMessage	-	-	-	-	0	0	0	-	-	-	-	-	Covered	T4,T5,T9
StMessageWait	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T4,T5,T9
StMessageWait	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T4,T5,T9
StPad	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T4,T5,T9
StPad	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T4,T5,T9
StPad	-	-	-	-	-	-	-	-	0	0	-	-	Not Covered
StPadRun	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T9
StPad01	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T4,T5,T9
StPad01	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T4,T5,T9
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T5,T9
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T5,T9
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	493	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T6,T11,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	557	case (mode_i)

Branches:

-1-	Status	Tests
Sha3	Covered	T4,T5,T6
Shake	Covered	T4,T28,T9
CShake	Covered	T4,T11,T28
default	Not Covered

	LineNo.	Expression
-1-:	590	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T4,T5,T9
MuxPrefix	Covered	T4,T11,T9
MuxFuncPad	Covered	T4,T5,T9
MuxZeroEnd	Covered	T4,T5,T9
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	602	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T4,T5,T9
MuxPrefix	Covered	T4,T11,T9
MuxFuncPad	Covered	T4,T5,T9
MuxZeroEnd	Covered	T4,T5,T9
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	614	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T4,T5,T9
MuxPrefix	Covered	T4,T11,T9
MuxFuncPad	Covered	T4,T5,T9
MuxZeroEnd	Covered	T4,T5,T9
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	663	if ((!rst_ni))
-2-:	666	if (en_msgbuf)
-3-:	671	if (clr_msgbuf)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T9
0	0	1	Covered	T4,T5,T9
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	778	if ((!rst_ni))
-2-:	780	if (start_i)
-3-:	782	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T11
0	0	1	Covered	T4,T5,T9
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	787	if ((!rst_ni))
-2-:	789	if (start_i)
-3-:	791	if (process_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T11
0	0	1	Covered	T4,T5,T9
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	797	if ((!rst_ni))
-2-:	799	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_o))
-3-:	801	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T9
0	0	1	Covered	T4,T5,T9
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	679	case (msg_strb)

Branches:

-1-	Status	Tests
7'b0000000	Covered	T4,T5,T6
7'b0000001	Covered	T4,T5,T9
7'b0000011	Covered	T4,T5,T9
7'b0000111	Covered	T4,T5,T9
7'b0001111	Covered	T4,T5,T9
7'b0011111	Covered	T4,T5,T9
7'b0111111	Covered	T4,T5,T9
7'b1111111	Covered	T4,T5,T9
default	Not Covered

---

Assert Coverage for Instance : tb.dut.u_sha3.u_pad

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	4	4	100.00	4	100.00
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AbsorbedPulse_A	2147483647	345696	0	0
AlwaysPartialMsgBuf_M	2147483647	197764	0	0
CompleteBlockWhenProcess_A	2147483647	333571	0	0
DoneCondition_M	2147483647	345679	0	0
DonePulse_A	2147483647	345679	0	0
KeccakAddrInRange_A	2147483647	53010624	0	0
KeccakRunPulse_A	2147483647	3073126	0	0
MessageCondition_M	2147483647	48277822	0	0
ModeStableDuringOp_M	2147483647	35401	0	0
MsgReadyCondition_A	2147483647	2132388043	0	0
MsgWidthidth_A	1048	1048	0	0
NoPartialMsgFifo_M	2147483647	48080058	0	0
Pad01NotAttheEndOfBlock_A	2147483647	335022	0	0
PartialEndOfMsg_M	2147483647	197764	0	0
PrefixLessThanBlock_A	1048	1048	0	0
ProcessCondition_M	2147483647	345698	0	0
ProcessPulse_A	2147483647	345698	0	0
StartCondition_M	2147483647	345816	0	0
StartProcessDoneMutex_a	2147483647	2147483647	0	0
StartPulse_A	2147483647	345816	0	0
StrengthStableDuringOp_M	2147483647	42345	0	0
u_state_regs_A	2147483647	2147483647	0	0

AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345696	0	0
T4	433149	97	0	0
T5	150232	310	0	0
T6	365006	0	0	0
T9	159318	45	0	0
T10	250375	177	0	0
T11	4277	0	0	0
T13	0	173	0	0
T23	0	9	0	0
T28	69577	0	0	0
T29	17129	9	0	0
T30	26458	9	0	0
T31	475078	310	0	0
T38	0	2337	0	0

AlwaysPartialMsgBuf_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	197764	0	0
T4	433149	83	0	0
T5	150232	270	0	0
T6	365006	0	0	0
T9	159318	41	0	0
T10	250375	150	0	0
T11	4277	0	0	0
T13	0	158	0	0
T23	0	9	0	0
T28	69577	0	0	0
T29	17129	8	0	0
T30	26458	9	0	0
T31	475078	270	0	0
T38	0	1058	0	0

CompleteBlockWhenProcess_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	333571	0	0
T4	433149	95	0	0
T5	150232	287	0	0
T6	365006	0	0	0
T9	159318	41	0	0
T10	250375	164	0	0
T11	4277	0	0	0
T13	0	170	0	0
T23	0	9	0	0
T28	69577	0	0	0
T29	17129	9	0	0
T30	26458	9	0	0
T31	475078	287	0	0
T38	0	2283	0	0

DoneCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345679	0	0
T4	433149	97	0	0
T5	150232	310	0	0
T6	365006	0	0	0
T9	159318	45	0	0
T10	250375	177	0	0
T11	4277	0	0	0
T13	0	173	0	0
T23	0	9	0	0
T28	69577	0	0	0
T29	17129	9	0	0
T30	26458	9	0	0
T31	475078	310	0	0
T38	0	2337	0	0

DonePulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345679	0	0
T4	433149	97	0	0
T5	150232	310	0	0
T6	365006	0	0	0
T9	159318	45	0	0
T10	250375	177	0	0
T11	4277	0	0	0
T13	0	173	0	0
T23	0	9	0	0
T28	69577	0	0	0
T29	17129	9	0	0
T30	26458	9	0	0
T31	475078	310	0	0
T38	0	2337	0	0

KeccakAddrInRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	53010624	0	0
T4	433149	67471	0	0
T5	150232	71006	0	0
T6	365006	0	0	0
T9	159318	7663	0	0
T10	250375	120275	0	0
T11	4277	17	0	0
T13	0	31193	0	0
T28	69577	0	0	0
T29	17129	385	0	0
T30	26458	607	0	0
T31	475078	71006	0	0
T38	0	276087	0	0

KeccakRunPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3073126	0	0
T4	433149	3615	0	0
T5	150232	5462	0	0
T6	365006	0	0	0
T9	159318	395	0	0
T10	250375	6391	0	0
T11	4277	1	0	0
T13	0	1675	0	0
T28	69577	0	0	0
T29	17129	21	0	0
T30	26458	31	0	0
T31	475078	5462	0	0
T38	0	13147	0	0

MessageCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48277822	0	0
T4	433149	64930	0	0
T5	150232	69082	0	0
T6	365006	0	0	0
T9	159318	6387	0	0
T10	250375	116144	0	0
T11	4277	0	0	0
T13	0	26216	0	0
T23	0	286	0	0
T28	69577	0	0	0
T29	17129	133	0	0
T30	26458	286	0	0
T31	475078	69082	0	0
T38	0	241576	0	0

ModeStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35401	0	0
T4	433149	31	0	0
T5	150232	0	0	0
T6	365006	0	0	0
T9	159318	20	0	0
T10	250375	68	0	0
T11	4277	1	0	0
T13	0	80	0	0
T23	0	1	0	0
T28	69577	31	0	0
T29	17129	5	0	0
T30	26458	1	0	0
T31	475078	0	0	0
T38	0	1	0	0

MsgReadyCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2132388043	0	0
T4	433149	361965	0	0
T5	150232	766401	0	0
T6	365006	0	0	0
T9	159318	702535	0	0
T10	250375	120166	0	0
T11	4277	0	0	0
T13	0	767432	0	0
T23	0	8355	0	0
T28	69577	0	0	0
T29	17129	1120	0	0
T30	26458	9228	0	0
T31	475078	397460	0	0
T38	0	341707	0	0

MsgWidthidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1048	1048	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0

NoPartialMsgFifo_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48080058	0	0
T4	433149	64847	0	0
T5	150232	68812	0	0
T6	365006	0	0	0
T9	159318	6346	0	0
T10	250375	115994	0	0
T11	4277	0	0	0
T13	0	26058	0	0
T23	0	277	0	0
T28	69577	0	0	0
T29	17129	125	0	0
T30	26458	277	0	0
T31	475078	68812	0	0
T38	0	240518	0	0

Pad01NotAttheEndOfBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	335022	0	0
T4	433149	96	0	0
T5	150232	289	0	0
T6	365006	0	0	0
T9	159318	41	0	0
T10	250375	167	0	0
T11	4277	0	0	0
T13	0	171	0	0
T23	0	9	0	0
T28	69577	0	0	0
T29	17129	9	0	0
T30	26458	9	0	0
T31	475078	289	0	0
T38	0	2289	0	0

PartialEndOfMsg_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	197764	0	0
T4	433149	83	0	0
T5	150232	270	0	0
T6	365006	0	0	0
T9	159318	41	0	0
T10	250375	150	0	0
T11	4277	0	0	0
T13	0	158	0	0
T23	0	9	0	0
T28	69577	0	0	0
T29	17129	8	0	0
T30	26458	9	0	0
T31	475078	270	0	0
T38	0	1058	0	0

PrefixLessThanBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1048	1048	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0

ProcessCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345698	0	0
T4	433149	97	0	0
T5	150232	310	0	0
T6	365006	0	0	0
T9	159318	45	0	0
T10	250375	177	0	0
T11	4277	0	0	0
T13	0	173	0	0
T23	0	9	0	0
T28	69577	0	0	0
T29	17129	9	0	0
T30	26458	9	0	0
T31	475078	310	0	0
T38	0	2337	0	0

ProcessPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345698	0	0
T4	433149	97	0	0
T5	150232	310	0	0
T6	365006	0	0	0
T9	159318	45	0	0
T10	250375	177	0	0
T11	4277	0	0	0
T13	0	173	0	0
T23	0	9	0	0
T28	69577	0	0	0
T29	17129	9	0	0
T30	26458	9	0	0
T31	475078	310	0	0
T38	0	2337	0	0

StartCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345816	0	0
T4	433149	97	0	0
T5	150232	310	0	0
T6	365006	0	0	0
T9	159318	47	0	0
T10	250375	177	0	0
T11	4277	1	0	0
T13	0	177	0	0
T28	69577	0	0	0
T29	17129	9	0	0
T30	26458	9	0	0
T31	475078	310	0	0
T38	0	2337	0	0

StartProcessDoneMutex_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	433149	433143	0	0
T5	150232	150225	0	0
T6	365006	351920	0	0
T9	159318	159306	0	0
T10	250375	250366	0	0
T11	4277	4100	0	0
T28	69577	69519	0	0
T29	17129	17072	0	0
T30	26458	26399	0	0
T31	475078	475073	0	0

StartPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345816	0	0
T4	433149	97	0	0
T5	150232	310	0	0
T6	365006	0	0	0
T9	159318	47	0	0
T10	250375	177	0	0
T11	4277	1	0	0
T13	0	177	0	0
T28	69577	0	0	0
T29	17129	9	0	0
T30	26458	9	0	0
T31	475078	310	0	0
T38	0	2337	0	0

StrengthStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	42345	0	0
T4	433149	54	0	0
T5	150232	2	0	0
T6	365006	171	0	0
T9	159318	31	0	0
T10	250375	90	0	0
T11	4277	3	0	0
T28	69577	25	0	0
T29	17129	6	0	0
T30	26458	2	0	0
T31	475078	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	433149	433143	0	0
T5	150232	150225	0	0
T6	365006	351920	0	0
T9	159318	159306	0	0
T10	250375	250366	0	0
T11	4277	4100	0	0
T28	69577	69519	0	0
T29	17129	17072	0	0
T30	26458	26399	0	0
T31	475078	475073	0	0

---

Cover Directives for Properties: Details

Name	Attempts	Matches	Incomplete
StComplete_C	2147483647	33566900	0
StMessageFeed_C	2147483647	2135421830	0
StPadSendMsg_C	2147483647	3843417	0
StPad_C	2147483647	335021	0

StComplete_C

Name	Attempts	Matches	Incomplete
Total	2147483647	33566900	0
T4	433149	9409	0
T5	150232	30070	0
T6	365006	0	0
T9	159318	4365	0
T10	250375	17169	0
T11	4277	0	0
T13	0	16781	0
T23	0	873	0
T28	69577	0	0
T29	17129	873	0
T30	26458	873	0
T31	475078	30070	0
T38	0	226689	0

StMessageFeed_C

Name	Attempts	Matches	Incomplete
Total	2147483647	2135421830	0
T4	433149	362318	0
T5	150232	771863	0
T6	365006	0	0
T9	159318	702890	0
T10	250375	120792	0
T11	4277	0	0
T13	0	768962	0
T23	0	8377	0
T28	69577	0	0
T29	17129	1135	0
T30	26458	9250	0
T31	475078	398006	0
T38	0	343022	0

StPadSendMsg_C

Name	Attempts	Matches	Incomplete
Total	2147483647	3843417	0
T4	433149	974	0
T5	150232	1884	0
T6	365006	0	0
T9	159318	508	0
T10	250375	1642	0
T11	4277	0	0
T13	0	2221	0
T23	0	144	0
T28	69577	0	0
T29	17129	137	0
T30	26458	144	0
T31	475078	1884	0
T38	0	33232	0

StPad_C

Name	Attempts	Matches	Incomplete
Total	2147483647	335021	0
T4	433149	96	0
T5	150232	289	0
T6	365006	0	0
T9	159318	41	0
T10	250375	167	0
T11	4277	0	0
T13	0	171	0
T23	0	9	0
T28	69577	0	0
T29	17129	9	0
T30	26458	9	0
T31	475078	289	0
T38	0	2289	0