Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	115106586	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1263	1263	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	115106586	0	0
T56	1615	258	0	0
T57	1197	0	0	0
T58	8859	495	0	0
T59	12626	0	0	0
T60	1433	0	0	0
T61	7844	185	0	0
T62	6708	0	0	0
T63	0	82	0	0
T64	0	60	0	0
T65	0	895	0	0
T69	10404	0	0	0
T70	3008	0	0	0
T71	22258	0	0	0
T73	0	2	0	0
T74	0	318	0	0
T75	0	251	0	0
T76	0	405	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	832	761	0	0
T2	2174	2084	0	0
T3	2665	2195	0	0
T54	1499	1448	0	0
T55	1824	1732	0	0
T56	1615	1548	0	0
T57	1197	1105	0	0
T58	8859	8790	0	0
T59	12626	12488	0	0
T60	1433	1356	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	832	761	0	0
T2	2174	2084	0	0
T3	2665	2195	0	0
T54	1499	1448	0	0
T55	1824	1732	0	0
T56	1615	1548	0	0
T57	1197	1105	0	0
T58	8859	8790	0	0
T59	12626	12488	0	0
T60	1433	1356	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	832	761	0	0
T2	2174	2084	0	0
T3	2665	2195	0	0
T54	1499	1448	0	0
T55	1824	1732	0	0
T56	1615	1548	0	0
T57	1197	1105	0	0
T58	8859	8790	0	0
T59	12626	12488	0	0
T60	1433	1356	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1263	1263	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	203458665	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1263	1263	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	203458665	0	0
T56	1615	142	0	0
T57	1197	0	0	0
T58	8859	473	0	0
T59	12626	0	0	0
T60	1433	0	0	0
T61	7844	489	0	0
T62	6708	0	0	0
T63	0	77	0	0
T64	0	60	0	0
T65	0	501	0	0
T69	10404	0	0	0
T70	3008	0	0	0
T71	22258	0	0	0
T73	0	2	0	0
T74	0	174	0	0
T75	0	237	0	0
T76	0	752	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	832	761	0	0
T2	2174	2084	0	0
T3	2665	2195	0	0
T54	1499	1448	0	0
T55	1824	1732	0	0
T56	1615	1548	0	0
T57	1197	1105	0	0
T58	8859	8790	0	0
T59	12626	12488	0	0
T60	1433	1356	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	832	761	0	0
T2	2174	2084	0	0
T3	2665	2195	0	0
T54	1499	1448	0	0
T55	1824	1732	0	0
T56	1615	1548	0	0
T57	1197	1105	0	0
T58	8859	8790	0	0
T59	12626	12488	0	0
T60	1433	1356	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	832	761	0	0
T2	2174	2084	0	0
T3	2665	2195	0	0
T54	1499	1448	0	0
T55	1824	1732	0	0
T56	1615	1548	0	0
T57	1197	1105	0	0
T58	8859	8790	0	0
T59	12626	12488	0	0
T60	1433	1356	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1263	1263	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	321203201	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1263	1263	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	321203201	0	0
T1	832	22	0	0
T2	2174	1159	0	0
T3	2665	517	0	0
T54	1499	40	0	0
T55	1824	40	0	0
T56	1615	287	0	0
T57	1197	40	0	0
T58	8859	487	0	0
T59	12626	3791	0	0
T60	1433	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	832	761	0	0
T2	2174	2084	0	0
T3	2665	2195	0	0
T54	1499	1448	0	0
T55	1824	1732	0	0
T56	1615	1548	0	0
T57	1197	1105	0	0
T58	8859	8790	0	0
T59	12626	12488	0	0
T60	1433	1356	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	832	761	0	0
T2	2174	2084	0	0
T3	2665	2195	0	0
T54	1499	1448	0	0
T55	1824	1732	0	0
T56	1615	1548	0	0
T57	1197	1105	0	0
T58	8859	8790	0	0
T59	12626	12488	0	0
T60	1433	1356	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	832	761	0	0
T2	2174	2084	0	0
T3	2665	2195	0	0
T54	1499	1448	0	0
T55	1824	1732	0	0
T56	1615	1548	0	0
T57	1197	1105	0	0
T58	8859	8790	0	0
T59	12626	12488	0	0
T60	1433	1356	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1263	1263	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	571858512	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1263	1263	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	571858512	0	0
T1	832	22	0	0
T2	2174	610	0	0
T3	2665	280	0	0
T54	1499	152	0	0
T55	1824	148	0	0
T56	1615	160	0	0
T57	1197	40	0	0
T58	8859	468	0	0
T59	12626	7365	0	0
T60	1433	108	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	832	761	0	0
T2	2174	2084	0	0
T3	2665	2195	0	0
T54	1499	1448	0	0
T55	1824	1732	0	0
T56	1615	1548	0	0
T57	1197	1105	0	0
T58	8859	8790	0	0
T59	12626	12488	0	0
T60	1433	1356	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	832	761	0	0
T2	2174	2084	0	0
T3	2665	2195	0	0
T54	1499	1448	0	0
T55	1824	1732	0	0
T56	1615	1548	0	0
T57	1197	1105	0	0
T58	8859	8790	0	0
T59	12626	12488	0	0
T60	1433	1356	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	832	761	0	0
T2	2174	2084	0	0
T3	2665	2195	0	0
T54	1499	1448	0	0
T55	1824	1732	0	0
T56	1615	1548	0	0
T57	1197	1105	0	0
T58	8859	8790	0	0
T59	12626	12488	0	0
T60	1433	1356	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1263	1263	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0