Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1529566	0	0
entropy_period_rd_A	2147483647	2361	0	0
intr_enable_rd_A	2147483647	2877	0	0
prefix_0_rd_A	2147483647	2146	0	0
prefix_10_rd_A	2147483647	2192	0	0
prefix_1_rd_A	2147483647	2206	0	0
prefix_2_rd_A	2147483647	2482	0	0
prefix_3_rd_A	2147483647	2396	0	0
prefix_4_rd_A	2147483647	2200	0	0
prefix_5_rd_A	2147483647	2271	0	0
prefix_6_rd_A	2147483647	2138	0	0
prefix_7_rd_A	2147483647	2287	0	0
prefix_8_rd_A	2147483647	2304	0	0
prefix_9_rd_A	2147483647	2278	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1529566	0	0
T58	8859	118	0	0
T59	12626	0	0	0
T60	1433	0	0	0
T61	7844	165	0	0
T62	6708	0	0	0
T63	2197	1	0	0
T64	0	133	0	0
T65	0	7	0	0
T67	0	183	0	0
T69	10404	0	0	0
T70	3008	0	0	0
T71	22258	2	0	0
T72	9765	0	0	0
T73	0	2	0	0
T104	0	1	0	0
T105	0	3	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2361	0	0
T59	12626	56	0	0
T60	1433	0	0	0
T61	7844	0	0	0
T62	6708	5	0	0
T63	2197	0	0	0
T69	10404	0	0	0
T70	3008	0	0	0
T71	22258	73	0	0
T72	9765	0	0	0
T85	4842	0	0	0
T91	0	95	0	0
T93	0	80	0	0
T95	0	36	0	0
T105	0	49	0	0
T108	0	5	0	0
T132	0	273	0	0
T133	0	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2877	0	0
T54	1499	30	0	0
T55	1824	32	0	0
T56	1615	0	0	0
T57	1197	0	0	0
T58	8859	0	0	0
T59	12626	53	0	0
T60	1433	17	0	0
T62	6708	28	0	0
T69	10404	0	0	0
T70	3008	0	0	0
T71	0	50	0	0
T91	0	156	0	0
T132	0	226	0	0
T133	0	13	0	0
T134	0	7	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2146	0	0
T59	12626	34	0	0
T60	1433	0	0	0
T61	7844	0	0	0
T62	6708	16	0	0
T63	2197	0	0	0
T69	10404	0	0	0
T70	3008	0	0	0
T71	22258	50	0	0
T72	9765	0	0	0
T85	4842	0	0	0
T91	0	67	0	0
T93	0	65	0	0
T95	0	32	0	0
T105	0	44	0	0
T119	0	6	0	0
T132	0	178	0	0
T133	0	3	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2192	0	0
T59	12626	4	0	0
T60	1433	0	0	0
T61	7844	0	0	0
T62	6708	29	0	0
T63	2197	0	0	0
T69	10404	0	0	0
T70	3008	0	0	0
T71	22258	95	0	0
T72	9765	0	0	0
T73	0	5	0	0
T85	4842	0	0	0
T91	0	51	0	0
T95	0	32	0	0
T108	0	7	0	0
T114	0	9	0	0
T132	0	203	0	0
T133	0	2	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2206	0	0
T59	12626	69	0	0
T60	1433	0	0	0
T61	7844	0	0	0
T62	6708	42	0	0
T63	2197	0	0	0
T69	10404	0	0	0
T70	3008	0	0	0
T71	22258	53	0	0
T72	9765	0	0	0
T85	4842	0	0	0
T91	0	77	0	0
T93	0	47	0	0
T95	0	44	0	0
T108	0	3	0	0
T114	0	7	0	0
T132	0	179	0	0
T133	0	5	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2482	0	0
T59	12626	77	0	0
T60	1433	0	0	0
T61	7844	0	0	0
T62	6708	45	0	0
T63	2197	0	0	0
T69	10404	0	0	0
T70	3008	0	0	0
T71	22258	58	0	0
T72	9765	0	0	0
T73	0	2	0	0
T85	4842	0	0	0
T91	0	90	0	0
T95	0	40	0	0
T108	0	1	0	0
T114	0	2	0	0
T132	0	272	0	0
T133	0	1	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2396	0	0
T59	12626	61	0	0
T60	1433	0	0	0
T61	7844	0	0	0
T62	6708	54	0	0
T63	2197	0	0	0
T69	10404	0	0	0
T70	3008	0	0	0
T71	22258	34	0	0
T72	9765	0	0	0
T85	4842	0	0	0
T91	0	68	0	0
T93	0	60	0	0
T95	0	27	0	0
T105	0	32	0	0
T114	0	4	0	0
T132	0	197	0	0
T133	0	5	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2200	0	0
T59	12626	60	0	0
T60	1433	0	0	0
T61	7844	0	0	0
T62	6708	3	0	0
T63	2197	0	0	0
T69	10404	0	0	0
T70	3008	0	0	0
T71	22258	65	0	0
T72	9765	0	0	0
T85	4842	0	0	0
T91	0	74	0	0
T93	0	59	0	0
T95	0	25	0	0
T108	0	1	0	0
T114	0	7	0	0
T132	0	227	0	0
T133	0	5	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2271	0	0
T59	12626	84	0	0
T60	1433	0	0	0
T61	7844	0	0	0
T62	6708	0	0	0
T63	2197	0	0	0
T69	10404	0	0	0
T70	3008	0	0	0
T71	22258	36	0	0
T72	9765	0	0	0
T85	4842	0	0	0
T91	0	47	0	0
T93	0	78	0	0
T95	0	43	0	0
T105	0	52	0	0
T108	0	9	0	0
T114	0	2	0	0
T132	0	242	0	0
T133	0	6	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2138	0	0
T59	12626	78	0	0
T60	1433	0	0	0
T61	7844	0	0	0
T62	6708	21	0	0
T63	2197	0	0	0
T69	10404	0	0	0
T70	3008	0	0	0
T71	22258	76	0	0
T72	9765	0	0	0
T85	4842	0	0	0
T91	0	68	0	0
T93	0	39	0	0
T95	0	30	0	0
T105	0	30	0	0
T114	0	7	0	0
T132	0	229	0	0
T133	0	9	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2287	0	0
T59	12626	44	0	0
T60	1433	0	0	0
T61	7844	0	0	0
T62	6708	43	0	0
T63	2197	0	0	0
T69	10404	0	0	0
T70	3008	0	0	0
T71	22258	41	0	0
T72	9765	0	0	0
T73	0	1	0	0
T85	4842	0	0	0
T91	0	82	0	0
T95	0	22	0	0
T108	0	1	0	0
T114	0	7	0	0
T132	0	265	0	0
T133	0	2	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2304	0	0
T59	12626	79	0	0
T60	1433	0	0	0
T61	7844	0	0	0
T62	6708	16	0	0
T63	2197	0	0	0
T69	10404	0	0	0
T70	3008	0	0	0
T71	22258	33	0	0
T72	9765	0	0	0
T85	4842	0	0	0
T91	0	59	0	0
T93	0	84	0	0
T95	0	30	0	0
T108	0	4	0	0
T114	0	8	0	0
T132	0	246	0	0
T133	0	7	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2278	0	0
T59	12626	79	0	0
T60	1433	0	0	0
T61	7844	0	0	0
T62	6708	10	0	0
T63	2197	0	0	0
T69	10404	0	0	0
T70	3008	0	0	0
T71	22258	43	0	0
T72	9765	0	0	0
T73	0	4	0	0
T85	4842	0	0	0
T91	0	76	0	0
T95	0	41	0	0
T108	0	3	0	0
T114	0	5	0	0
T132	0	251	0	0
T133	0	1	0	0