Unified Coverage Report :: Module :: prim_fifo_sync_cnt

Module : prim_fifo_sync_cnt

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.81	94.44	100.00			75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt	76.67	86.67				66.67
tb.dut.u_tlul_adapter_msgfifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt	76.67	86.67				66.67
tb.dut.u_tlul_adapter_msgfifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_staterd.u_tlul_adapter.u_reqfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_staterd.u_tlul_adapter.u_rspfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_msgfifo.u_msgfifo.gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00

---

Module Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.67	86.67				66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.67	86.67				66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
63.39	85.71	47.83			60.00	60.00	u_sramreqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.67	86.67				66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.67	86.67				66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
69.21	95.00	51.85			70.00	60.00	u_rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.77	100.00	73.08			90.00	100.00	u_reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.77	100.00	73.08			90.00	100.00	u_reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.81	100.00	69.23			90.00	100.00	u_sramreqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.03	100.00	76.47			91.67	100.00	u_rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_msgfifo.u_msgfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.79	100.00	91.18			100.00	100.00	u_msgfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_secure_ptrs.u_rptr	100.00			100.00
gen_secure_ptrs.u_wptr	100.00			100.00

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Width=2,Secure=0 )
Line Coverage for Module self-instances :

SCORE	LINE
81.94	88.89

tb.dut.u_tlul_adapter_msgfifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
76.67	86.67

tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
76.67	86.67

tb.dut.u_tlul_adapter_msgfifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
81.94	88.89

tb.dut.u_staterd.u_tlul_adapter.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
81.94	88.89

tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
81.94	88.89

tb.dut.u_staterd.u_tlul_adapter.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

---

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=10,Width=5,Secure=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_msgfifo.u_msgfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
70	1	1

---

Cond Coverage for Module : prim_fifo_sync_cnt

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       70
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

---

Branch Coverage for Module : prim_fifo_sync_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Unreachable
0	0	1	-	Covered	T5,T6,T10
0	0	0	1	Not Covered
0	0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Unreachable
0	0	1	-	Covered	T5,T6,T10
0	0	0	1	Not Covered
0	0	0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		15	13	86.67
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	5	71.43
ALWAYS	86	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30		unreachable
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	0	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91		unreachable
92	1	1
93		unreachable
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		6	4	66.67
IF	74	4	2	50.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Unreachable
0	0	1	-	Unreachable
0	0	0	1	Unreachable
0	0	0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		15	13	86.67
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	5	5	100.00
ALWAYS	86	7	5	71.43

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29		unreachable
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79		unreachable
80	1	1
81		unreachable
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	0	1
92	1	1
93	0	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		6	4	66.67
IF	74	2	2	100.00
IF	86	4	2	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Unreachable
0	0	1	-	Unreachable
0	0	0	1	Unreachable
0	0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Unreachable
0	0	1	-	Covered	T5,T6,T10
0	0	0	1	Not Covered
0	0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Unreachable
0	0	1	-	Covered	T5,T6,T10
0	0	0	1	Not Covered
0	0	0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Unreachable
0	0	1	-	Covered	T5,T6,T10
0	0	0	1	Not Covered
0	0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Unreachable
0	0	1	-	Covered	T5,T6,T10
0	0	0	1	Not Covered
0	0	0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Unreachable
0	0	1	-	Covered	T5,T6,T10
0	0	0	1	Not Covered
0	0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Unreachable
0	0	1	-	Covered	T5,T6,T10
0	0	0	1	Not Covered
0	0	0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Unreachable
0	0	1	-	Covered	T5,T6,T10
0	0	0	1	Not Covered
0	0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Unreachable
0	0	1	-	Covered	T5,T6,T10
0	0	0	1	Not Covered
0	0	0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
70	1	1

---

Cond Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       70
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9