Unified Coverage Report :: Module Instance :: tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

Module Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.77	100.00	73.08			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.85	95.00	73.08			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.00	98.41	76.70			79.17	85.71	u_tlul_adapter_msgfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00

Module Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.39	85.71	47.83			60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.11	86.11	47.83			62.50	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.00	98.41	76.70			79.17	85.71	u_tlul_adapter_msgfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	76.67	86.67				66.67

Module Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.21	95.00	51.85			70.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.01	91.43	51.85			68.75	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.00	98.41	76.70			79.17	85.71	u_tlul_adapter_msgfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	76.67	86.67				66.67

Module Instance : tb.dut.u_msgfifo.u_msgfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.79	100.00	91.18			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.21	100.00			100.00	92.86	100.00	u_msgfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00

Module Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.77	100.00	73.08			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.85	95.00	73.08			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.95	98.48	81.65			91.67	100.00	u_tlul_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00

Module Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.81	100.00	69.23			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.89	95.00	69.23			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.95	98.48	81.65			91.67	100.00	u_tlul_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00

Module Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.03	100.00	76.47			91.67	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.12	95.00	76.47			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.95	98.48	81.65			91.67	100.00	u_tlul_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
ALWAYS	157	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
154	1	1
157	1	1
158	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

	Total	Covered	Percent
Conditions	26	19	73.08
Logical	26	19	73.08
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T10

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T6

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T6,T10

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T6,T10
1	1	0	Not Covered
1	1	1	Covered	T5,T6,T10

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T10
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T5,T6,T10

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T10

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T5,T6,T10
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	88	3	2	66.67
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	157	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T10
0	1	Covered	T4,T5,T6
0	0	Not Covered

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T5,T6,T10

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T10
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	212135528	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2147483647	212135528	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	212135528	0	0
T5	550670	27790	0	0
T6	147141	158511	0	0
T10	6077	70	0	0
T11	202867	221129	0	0
T12	228444	101477	0	0
T13	2186	14	0	0
T14	5351	9	0	0
T32	365082	18196	0	0
T33	546213	25034	0	0
T34	671278	33243	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	1136	1077	0	0
T5	550670	550570	0	0
T6	147141	147133	0	0
T10	6077	5904	0	0
T11	202867	202862	0	0
T12	228444	228432	0	0
T13	2186	2041	0	0
T14	5351	5200	0	0
T32	365082	364990	0	0
T33	546213	546153	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	1136	1077	0	0
T5	550670	550570	0	0
T6	147141	147133	0	0
T10	6077	5904	0	0
T11	202867	202862	0	0
T12	228444	228432	0	0
T13	2186	2041	0	0
T14	5351	5200	0	0
T32	365082	364990	0	0
T33	546213	546153	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	1136	1077	0	0
T5	550670	550570	0	0
T6	147141	147133	0	0
T10	6077	5904	0	0
T11	202867	202862	0	0
T12	228444	228432	0	0
T13	2186	2041	0	0
T14	5351	5200	0	0
T32	365082	364990	0	0
T33	546213	546153	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	212135528	0	0
T5	550670	27790	0	0
T6	147141	158511	0	0
T10	6077	70	0	0
T11	202867	221129	0	0
T12	228444	101477	0	0
T13	2186	14	0	0
T14	5351	9	0	0
T32	365082	18196	0	0
T33	546213	25034	0	0
T34	671278	33243	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		21	18	85.71
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	0	0
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	154	1	0	0.00
ALWAYS	157	2	1	50.00
CONT_ASSIGN	175	1	0	0.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93		unreachable
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
154	0	1
157	1	1
158	0	1
			MISSING_ELSE
175	0	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo

	Total	Covered	Percent
Conditions	23	11	47.83
Logical	23	11	47.83
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T6

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Not Covered
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Not Covered

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		10	6	60.00
TERNARY	88	3	1	33.33
TERNARY	180	2	1	50.00
IF	70	3	3	100.00
IF	157	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T4,T5,T6
0	0	Not Covered

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	0	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2147483647	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	1136	1077	0	0
T5	550670	550570	0	0
T6	147141	147133	0	0
T10	6077	5904	0	0
T11	202867	202862	0	0
T12	228444	228432	0	0
T13	2186	2041	0	0
T14	5351	5200	0	0
T32	365082	364990	0	0
T33	546213	546153	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	1136	1077	0	0
T5	550670	550570	0	0
T6	147141	147133	0	0
T10	6077	5904	0	0
T11	202867	202862	0	0
T12	228444	228432	0	0
T13	2186	2041	0	0
T14	5351	5200	0	0
T32	365082	364990	0	0
T33	546213	546153	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	1136	1077	0	0
T5	550670	550570	0	0
T6	147141	147133	0	0
T10	6077	5904	0	0
T11	202867	202862	0	0
T12	228444	228432	0	0
T13	2186	2041	0	0
T14	5351	5200	0	0
T32	365082	364990	0	0
T33	546213	546153	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		20	19	95.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	154	1	0	0.00
ALWAYS	157	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92		unreachable
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
154	0	1
157	1	1
158		unreachable
			MISSING_ELSE
172	1	1
173	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo

	Total	Covered	Percent
Conditions	27	14	51.85
Logical	27	14	51.85
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T6

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Not Covered

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Unreachable

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Unreachable

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Covered	T4,T5,T6

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		10	7	70.00
TERNARY	88	3	1	33.33
TERNARY	172	1	1	100.00
TERNARY	180	2	1	50.00
IF	70	3	3	100.00
IF	157	1	1	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T4,T5,T6
0	0	Not Covered

	LineNo.	Expression
-1-:	172	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	0	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2147483647	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	1136	1077	0	0
T5	550670	550570	0	0
T6	147141	147133	0	0
T10	6077	5904	0	0
T11	202867	202862	0	0
T12	228444	228432	0	0
T13	2186	2041	0	0
T14	5351	5200	0	0
T32	365082	364990	0	0
T33	546213	546153	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	1136	1077	0	0
T5	550670	550570	0	0
T6	147141	147133	0	0
T10	6077	5904	0	0
T11	202867	202862	0	0
T12	228444	228432	0	0
T13	2186	2041	0	0
T14	5351	5200	0	0
T32	365082	364990	0	0
T33	546213	546153	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	1136	1077	0	0
T5	550670	550570	0	0
T6	147141	147133	0	0
T10	6077	5904	0	0
T11	202867	202862	0	0
T12	228444	228432	0	0
T13	2186	2041	0	0
T14	5351	5200	0	0
T32	365082	364990	0	0
T33	546213	546153	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

Line Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
172	1	1
173	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo

	Total	Covered	Percent
Conditions	34	31	91.18
Logical	34	31	91.18
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T13,T11

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T5,T6,T11
1	Covered	T4,T5,T6

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T5,T6,T11
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T13,T32,T33
1	1	0	Not Covered
1	1	1	Covered	T5,T6,T13

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T10
1	0	1	Covered	T5,T6,T13
1	1	0	Not Covered
1	1	1	Covered	T5,T6,T11

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T13,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T5,T6,T13

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T13,T11

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T13

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T13
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T13

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T11
1	0	Covered	T5,T6,T13
1	1	Covered	T4,T5,T6

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T5,T6,T13
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	88	3	3	100.00
TERNARY	172	2	2	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	157	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T13,T11
0	1	Covered	T4,T5,T6
0	0	Covered	T5,T6,T11

	LineNo.	Expression
-1-:	172	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T5,T6,T13

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T13
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	192874330	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2147483647	192874330	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	192874330	0	0
T5	550670	85236	0	0
T6	147141	484525	0	0
T10	6077	0	0	0
T11	202867	524362	0	0
T12	228444	143293	0	0
T13	2186	1725	0	0
T14	5351	121	0	0
T32	365082	58361	0	0
T33	546213	79654	0	0
T34	671278	24600	0	0
T35	0	14125	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	1136	1077	0	0
T5	550670	550570	0	0
T6	147141	147133	0	0
T10	6077	5904	0	0
T11	202867	202862	0	0
T12	228444	228432	0	0
T13	2186	2041	0	0
T14	5351	5200	0	0
T32	365082	364990	0	0
T33	546213	546153	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	1136	1077	0	0
T5	550670	550570	0	0
T6	147141	147133	0	0
T10	6077	5904	0	0
T11	202867	202862	0	0
T12	228444	228432	0	0
T13	2186	2041	0	0
T14	5351	5200	0	0
T32	365082	364990	0	0
T33	546213	546153	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	1136	1077	0	0
T5	550670	550570	0	0
T6	147141	147133	0	0
T10	6077	5904	0	0
T11	202867	202862	0	0
T12	228444	228432	0	0
T13	2186	2041	0	0
T14	5351	5200	0	0
T32	365082	364990	0	0
T33	546213	546153	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	192874330	0	0
T5	550670	85236	0	0
T6	147141	484525	0	0
T10	6077	0	0	0
T11	202867	524362	0	0
T12	228444	143293	0	0
T13	2186	1725	0	0
T14	5351	121	0	0
T32	365082	58361	0	0
T33	546213	79654	0	0
T34	671278	24600	0	0
T35	0	14125	0	0

Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
ALWAYS	157	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
154	1	1
157	1	1
158	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo

	Total	Covered	Percent
Conditions	26	19	73.08
Logical	26	19	73.08
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T10

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T6

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T6,T10

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T6,T10
1	1	0	Not Covered
1	1	1	Covered	T5,T6,T10

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T10
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T5,T6,T10

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T10

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T5,T6,T10
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	88	3	2	66.67
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	157	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T10
0	1	Covered	T4,T5,T6
0	0	Not Covered

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T5,T6,T10

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T10
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	46897316	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2147483647	46897316	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	46897316	0	0
T5	550670	61330	0	0
T6	147141	7440	0	0
T10	6077	239	0	0
T11	202867	48212	0	0
T12	228444	68898	0	0
T13	2186	84	0	0
T14	5351	304	0	0
T32	365082	37480	0	0
T33	546213	57370	0	0
T34	671278	77325	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	1136	1077	0	0
T5	550670	550570	0	0
T6	147141	147133	0	0
T10	6077	5904	0	0
T11	202867	202862	0	0
T12	228444	228432	0	0
T13	2186	2041	0	0
T14	5351	5200	0	0
T32	365082	364990	0	0
T33	546213	546153	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	1136	1077	0	0
T5	550670	550570	0	0
T6	147141	147133	0	0
T10	6077	5904	0	0
T11	202867	202862	0	0
T12	228444	228432	0	0
T13	2186	2041	0	0
T14	5351	5200	0	0
T32	365082	364990	0	0
T33	546213	546153	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	1136	1077	0	0
T5	550670	550570	0	0
T6	147141	147133	0	0
T10	6077	5904	0	0
T11	202867	202862	0	0
T12	228444	228432	0	0
T13	2186	2041	0	0
T14	5351	5200	0	0
T32	365082	364990	0	0
T33	546213	546153	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	46897316	0	0
T5	550670	61330	0	0
T6	147141	7440	0	0
T10	6077	239	0	0
T11	202867	48212	0	0
T12	228444	68898	0	0
T13	2186	84	0	0
T14	5351	304	0	0
T32	365082	37480	0	0
T33	546213	57370	0	0
T34	671278	77325	0	0

Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
ALWAYS	157	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
154	1	1
157	1	1
158	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo

	Total	Covered	Percent
Conditions	26	18	69.23
Logical	26	18	69.23
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T10

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T6

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T6,T10

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T6,T10

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T10
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T5,T6,T10

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T10

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T5,T6,T10
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	88	3	2	66.67
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	157	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T10
0	1	Covered	T4,T5,T6
0	0	Not Covered

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T5,T6,T10

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T10
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	22158414	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2147483647	22158414	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22158414	0	0
T5	550670	61330	0	0
T6	147141	7440	0	0
T10	6077	84	0	0
T11	202867	48212	0	0
T12	228444	31048	0	0
T13	2186	84	0	0
T14	5351	68	0	0
T32	365082	37480	0	0
T33	546213	57370	0	0
T34	671278	17254	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	1136	1077	0	0
T5	550670	550570	0	0
T6	147141	147133	0	0
T10	6077	5904	0	0
T11	202867	202862	0	0
T12	228444	228432	0	0
T13	2186	2041	0	0
T14	5351	5200	0	0
T32	365082	364990	0	0
T33	546213	546153	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	1136	1077	0	0
T5	550670	550570	0	0
T6	147141	147133	0	0
T10	6077	5904	0	0
T11	202867	202862	0	0
T12	228444	228432	0	0
T13	2186	2041	0	0
T14	5351	5200	0	0
T32	365082	364990	0	0
T33	546213	546153	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	1136	1077	0	0
T5	550670	550570	0	0
T6	147141	147133	0	0
T10	6077	5904	0	0
T11	202867	202862	0	0
T12	228444	228432	0	0
T13	2186	2041	0	0
T14	5351	5200	0	0
T32	365082	364990	0	0
T33	546213	546153	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22158414	0	0
T5	550670	61330	0	0
T6	147141	7440	0	0
T10	6077	84	0	0
T11	202867	48212	0	0
T12	228444	31048	0	0
T13	2186	84	0	0
T14	5351	68	0	0
T32	365082	37480	0	0
T33	546213	57370	0	0
T34	671278	17254	0	0

Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
ALWAYS	157	2	2	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
154	1	1
157	1	1
158	1	1
			MISSING_ELSE
172	1	1
173	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo

	Total	Covered	Percent
Conditions	34	26	76.47
Logical	34	26	76.47
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T14,T34

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T6

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T6,T10

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T6,T10
1	1	0	Not Covered
1	1	1	Covered	T5,T6,T10

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T14,T34
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T5,T6,T10

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T14,T34

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T10

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T10

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T10,T14,T34
1	0	Covered	T5,T6,T10
1	1	Covered	T4,T5,T6

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T5,T6,T10
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		12	11	91.67
TERNARY	88	3	2	66.67
TERNARY	172	2	2	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	157	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T10,T14,T34
0	1	Covered	T4,T5,T6
0	0	Not Covered

	LineNo.	Expression
-1-:	172	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T5,T6,T10

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T10
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	43515218	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2147483647	43515218	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	43515218	0	0
T5	550670	61330	0	0
T6	147141	7440	0	0
T10	6077	239	0	0
T11	202867	48212	0	0
T12	228444	31048	0	0
T13	2186	84	0	0
T14	5351	304	0	0
T32	365082	37480	0	0
T33	546213	57370	0	0
T34	671278	77325	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	1136	1077	0	0
T5	550670	550570	0	0
T6	147141	147133	0	0
T10	6077	5904	0	0
T11	202867	202862	0	0
T12	228444	228432	0	0
T13	2186	2041	0	0
T14	5351	5200	0	0
T32	365082	364990	0	0
T33	546213	546153	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	1136	1077	0	0
T5	550670	550570	0	0
T6	147141	147133	0	0
T10	6077	5904	0	0
T11	202867	202862	0	0
T12	228444	228432	0	0
T13	2186	2041	0	0
T14	5351	5200	0	0
T32	365082	364990	0	0
T33	546213	546153	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	1136	1077	0	0
T5	550670	550570	0	0
T6	147141	147133	0	0
T10	6077	5904	0	0
T11	202867	202862	0	0
T12	228444	228432	0	0
T13	2186	2041	0	0
T14	5351	5200	0	0
T32	365082	364990	0	0
T33	546213	546153	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	43515218	0	0
T5	550670	61330	0	0
T6	147141	7440	0	0
T10	6077	239	0	0
T11	202867	48212	0	0
T12	228444	31048	0	0
T13	2186	84	0	0
T14	5351	304	0	0
T32	365082	37480	0	0
T33	546213	57370	0	0
T34	671278	77325	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	482711226	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1258	1258	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	482711226	0	0
T1	2812	524	0	0
T2	24774	2974	0	0
T3	2503	1218	0	0
T58	946	22	0	0
T59	15541	13813	0	0
T60	1034	1	0	0
T61	6100	1359	0	0
T62	2518	234	0	0
T63	19877	2981	0	0
T64	1781	514	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2812	2320	0	0
T2	24774	23174	0	0
T3	2503	2269	0	0
T58	946	886	0	0
T59	15541	15485	0	0
T60	1034	984	0	0
T61	6100	6014	0	0
T62	2518	2423	0	0
T63	19877	18276	0	0
T64	1781	1697	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2812	2320	0	0
T2	24774	23174	0	0
T3	2503	2269	0	0
T58	946	886	0	0
T59	15541	15485	0	0
T60	1034	984	0	0
T61	6100	6014	0	0
T62	2518	2423	0	0
T63	19877	18276	0	0
T64	1781	1697	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2812	2320	0	0
T2	24774	23174	0	0
T3	2503	2269	0	0
T58	946	886	0	0
T59	15541	15485	0	0
T60	1034	984	0	0
T61	6100	6014	0	0
T62	2518	2423	0	0
T63	19877	18276	0	0
T64	1781	1697	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1258	1258	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	856681703	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1258	1258	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	856681703	0	0
T1	2812	287	0	0
T2	24774	2732	0	0
T3	2503	625	0	0
T58	946	22	0	0
T59	15541	6965	0	0
T60	1034	1	0	0
T61	6100	2272	0	0
T62	2518	215	0	0
T63	19877	2721	0	0
T64	1781	268	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2812	2320	0	0
T2	24774	23174	0	0
T3	2503	2269	0	0
T58	946	886	0	0
T59	15541	15485	0	0
T60	1034	984	0	0
T61	6100	6014	0	0
T62	2518	2423	0	0
T63	19877	18276	0	0
T64	1781	1697	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2812	2320	0	0
T2	24774	23174	0	0
T3	2503	2269	0	0
T58	946	886	0	0
T59	15541	15485	0	0
T60	1034	984	0	0
T61	6100	6014	0	0
T62	2518	2423	0	0
T63	19877	18276	0	0
T64	1781	1697	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2812	2320	0	0
T2	24774	23174	0	0
T3	2503	2269	0	0
T58	946	886	0	0
T59	15541	15485	0	0
T60	1034	984	0	0
T61	6100	6014	0	0
T62	2518	2423	0	0
T63	19877	18276	0	0
T64	1781	1697	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1258	1258	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	24664730	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1258	1258	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	24664730	0	0
T5	0	61330	0	0
T61	6100	100	0	0
T62	2518	2	0	0
T63	19877	0	0	0
T64	1781	0	0	0
T65	3060	176	0	0
T66	12197	0	0	0
T67	0	537	0	0
T68	0	23	0	0
T69	0	488	0	0
T70	0	1	0	0
T71	0	129	0	0
T72	0	34	0	0
T73	3017	0	0	0
T74	4640	0	0	0
T75	1571	0	0	0
T76	1890	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2812	2320	0	0
T2	24774	23174	0	0
T3	2503	2269	0	0
T58	946	886	0	0
T59	15541	15485	0	0
T60	1034	984	0	0
T61	6100	6014	0	0
T62	2518	2423	0	0
T63	19877	18276	0	0
T64	1781	1697	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2812	2320	0	0
T2	24774	23174	0	0
T3	2503	2269	0	0
T58	946	886	0	0
T59	15541	15485	0	0
T60	1034	984	0	0
T61	6100	6014	0	0
T62	2518	2423	0	0
T63	19877	18276	0	0
T64	1781	1697	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2812	2320	0	0
T2	24774	23174	0	0
T3	2503	2269	0	0
T58	946	886	0	0
T59	15541	15485	0	0
T60	1034	984	0	0
T61	6100	6014	0	0
T62	2518	2423	0	0
T63	19877	18276	0	0
T64	1781	1697	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1258	1258	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	46904217	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1258	1258	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	46904217	0	0
T5	0	61330	0	0
T61	6100	249	0	0
T62	2518	2	0	0
T63	19877	0	0	0
T64	1781	0	0	0
T65	3060	145	0	0
T66	12197	0	0	0
T67	0	379	0	0
T68	0	17	0	0
T69	0	357	0	0
T70	0	1	0	0
T71	0	114	0	0
T72	0	30	0	0
T73	3017	0	0	0
T74	4640	0	0	0
T75	1571	0	0	0
T76	1890	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2812	2320	0	0
T2	24774	23174	0	0
T3	2503	2269	0	0
T58	946	886	0	0
T59	15541	15485	0	0
T60	1034	984	0	0
T61	6100	6014	0	0
T62	2518	2423	0	0
T63	19877	18276	0	0
T64	1781	1697	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2812	2320	0	0
T2	24774	23174	0	0
T3	2503	2269	0	0
T58	946	886	0	0
T59	15541	15485	0	0
T60	1034	984	0	0
T61	6100	6014	0	0
T62	2518	2423	0	0
T63	19877	18276	0	0
T64	1781	1697	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2812	2320	0	0
T2	24774	23174	0	0
T3	2503	2269	0	0
T58	946	886	0	0
T59	15541	15485	0	0
T60	1034	984	0	0
T61	6100	6014	0	0
T62	2518	2423	0	0
T63	19877	18276	0	0
T64	1781	1697	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1258	1258	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0