Module Definition
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Module : prim_fifo_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.12 100.00 77.49 95.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo 63.39 85.71 47.83 60.00 60.00
tb.dut.u_tlul_adapter_msgfifo.u_rspfifo 69.21 95.00 51.85 70.00 60.00
tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo 89.81 100.00 69.23 90.00 100.00
tb.dut.u_tlul_adapter_msgfifo.u_reqfifo 90.77 100.00 73.08 90.00 100.00
tb.dut.u_staterd.u_tlul_adapter.u_reqfifo 90.77 100.00 73.08 90.00 100.00
tb.dut.u_staterd.u_tlul_adapter.u_rspfifo 92.03 100.00 76.47 91.67 100.00
tb.dut.u_msgfifo.u_msgfifo 97.79 100.00 91.18 100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo 100.00 100.00 100.00

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Line Coverage for Module self-instances :
SCORELINE
90.77 100.00
tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

SCORELINE
63.39 85.71
tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo

SCORELINE
90.77 100.00
tb.dut.u_staterd.u_tlul_adapter.u_reqfifo

SCORELINE
89.81 100.00
tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo

Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN15411100.00
ALWAYS15722100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
154 1 1
157 1 1
158 1 1
MISSING_ELSE
175 1 1
176 1 1
180 1 1

Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Line Coverage for Module self-instances :
SCORELINE
69.21 95.00
tb.dut.u_tlul_adapter_msgfifo.u_rspfifo

SCORELINE
92.03 100.00
tb.dut.u_staterd.u_tlul_adapter.u_rspfifo

Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN15411100.00
ALWAYS15722100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
154 1 1
157 1 1
158 1 1
MISSING_ELSE
172 1 1
173 1 1
180 1 1

Line Coverage for Module : prim_fifo_sync ( parameter Width=72,Pass=1,Depth=10,OutputZeroIfEmpty=1,Secure=1,DepthW=4,gen_normal_fifo.PTRV_W=4,gen_normal_fifo.PTR_WIDTH=5 )
Line Coverage for Module self-instances :
SCORELINE
97.79 100.00
tb.dut.u_msgfifo.u_msgfifo

Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN16211100.00
ALWAYS16522100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
162 1 1
165 1 1
166 1 1
MISSING_ELSE
172 1 1
173 1 1
180 1 1

Line Coverage for Module : prim_fifo_sync ( parameter Width=109,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
SCORECOND
63.39 47.83
tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo

SCORECOND
89.81 69.23
tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo

TotalCoveredPercent
Conditions261869.23
Logical261869.23
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT4,T5,T6 

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1CoveredT4,T5,T6 

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101Not Covered
110Not Covered
111CoveredT4,T5,T6 

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT4,T5,T6 

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6 

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11CoveredT4,T5,T6 

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6
Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
SCORECOND
69.21 51.85
tb.dut.u_tlul_adapter_msgfifo.u_rspfifo

SCORECOND
92.03 76.47
tb.dut.u_staterd.u_tlul_adapter.u_rspfifo

TotalCoveredPercent
Conditions342676.47
Logical342676.47
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T11 

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT4,T5,T6 

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1CoveredT4,T5,T6 

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101Not Covered
110Not Covered
111CoveredT4,T5,T6 

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T5,T11
110Not Covered
111CoveredT4,T5,T6 

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T11
10CoveredT4,T5,T6
11CoveredT4,T5,T6 

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11CoveredT4,T5,T6 

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T11 

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11CoveredT4,T5,T6 

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT4,T5,T11
10CoveredT4,T5,T6
11CoveredT4,T5,T6 

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6
Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
SCORECOND
90.77 73.08
tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

SCORECOND
90.77 73.08
tb.dut.u_staterd.u_tlul_adapter.u_reqfifo

TotalCoveredPercent
Conditions261973.08
Logical261973.08
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT4,T5,T6 

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1CoveredT4,T5,T6 

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101Not Covered
110Not Covered
111CoveredT4,T5,T6 

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T5,T11
110Not Covered
111CoveredT4,T5,T6 

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6 

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11CoveredT4,T5,T6 

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6
Cond Coverage for Module : prim_fifo_sync ( parameter Width=72,Pass=1,Depth=10,OutputZeroIfEmpty=1,Secure=1,DepthW=4,gen_normal_fifo.PTRV_W=4,gen_normal_fifo.PTR_WIDTH=5 )
Cond Coverage for Module self-instances :
SCORECOND
97.79 91.18
tb.dut.u_msgfifo.u_msgfifo

TotalCoveredPercent
Conditions343191.18
Logical343191.18
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T6,T10 

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0CoveredT4,T6,T32
1CoveredT4,T5,T6 

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0CoveredT4,T6,T32
1CoveredT4,T5,T6 

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT4,T6,T41
110Not Covered
111CoveredT4,T5,T6 

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT4,T5,T6
110Not Covered
111CoveredT4,T5,T6 

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T6,T10
10CoveredT4,T5,T6
11CoveredT4,T5,T6 

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11CoveredT4,T5,T6 

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T6,T10 

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6 

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6 

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6
Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Branch Coverage for Module self-instances :
SCOREBRANCH
90.77 90.00
tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

SCOREBRANCH
90.77 90.00
tb.dut.u_staterd.u_tlul_adapter.u_reqfifo

SCOREBRANCH
63.39 60.00
tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo

SCOREBRANCH
89.81 90.00
tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo

Line No.TotalCoveredPercent
Branches 10 9 90.00
TERNARY 88 3 2 66.67
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 157 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Not Covered 



	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=72,Pass=1,Depth=10,OutputZeroIfEmpty=1,Secure=1,DepthW=4,gen_normal_fifo.PTRV_W=4,gen_normal_fifo.PTR_WIDTH=5 )
Branch Coverage for Module self-instances :
SCOREBRANCH
69.21 70.00
tb.dut.u_tlul_adapter_msgfifo.u_rspfifo

SCOREBRANCH
92.03 91.67
tb.dut.u_staterd.u_tlul_adapter.u_rspfifo

SCOREBRANCH
97.79 100.00
tb.dut.u_msgfifo.u_msgfifo

Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 88 3 3 100.00
TERNARY 172 2 2 100.00
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 157 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Covered T4,T6,T32 



	LineNo.	Expression
-1-:	172	((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 2147483647 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 2147483647 539591562 0 0
gen_passthru_fifo.paramCheckPass 10160 10160 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 308664 81005 0 0
T2 3384 708 0 0
T3 1758 76 0 0
T4 884963 54013 0 0
T5 386719 25010 0 0
T6 271688 29955 0 0
T10 391902 59645 0 0
T11 3079 69 0 0
T12 3141 2 0 0
T32 641204 281938 0 0
T33 176134 626200 0 0
T34 172728 638510 0 0
T35 669296 272811 0 0
T61 12972 3488 0 0
T62 56306 5750 0 0
T63 3222 210 0 0
T64 4648 548 0 0
T65 5980 1835 0 0
T66 3158 277 0 0
T67 19635 1973 0 0
T68 0 439 0 0
T69 1371 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 1234656 1234152 0 0
T2 13536 13000 0 0
T3 7032 6576 0 0
T4 6194741 6194104 0 0
T5 2707033 2706473 0 0
T6 1901816 1901270 0 0
T10 2743314 2742614 0 0
T11 21553 20587 0 0
T12 21987 21021 0 0
T32 4488428 4488393 0 0
T33 1232938 1232938 0 0
T34 1209096 1209089 0 0
T35 4685072 4685023 0 0
T61 51888 49712 0 0
T62 225224 213200 0 0
T63 12888 12136 0 0
T64 18592 17824 0 0
T65 23920 23352 0 0
T66 12632 11808 0 0
T67 52360 51688 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 1234656 1234152 0 0
T2 13536 13000 0 0
T3 7032 6576 0 0
T4 6194741 6194104 0 0
T5 2707033 2706473 0 0
T6 1901816 1901270 0 0
T10 2743314 2742614 0 0
T11 21553 20587 0 0
T12 21987 21021 0 0
T32 4488428 4488393 0 0
T33 1232938 1232938 0 0
T34 1209096 1209089 0 0
T35 4685072 4685023 0 0
T61 51888 49712 0 0
T62 225224 213200 0 0
T63 12888 12136 0 0
T64 18592 17824 0 0
T65 23920 23352 0 0
T66 12632 11808 0 0
T67 52360 51688 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 1234656 1234152 0 0
T2 13536 13000 0 0
T3 7032 6576 0 0
T4 6194741 6194104 0 0
T5 2707033 2706473 0 0
T6 1901816 1901270 0 0
T10 2743314 2742614 0 0
T11 21553 20587 0 0
T12 21987 21021 0 0
T32 4488428 4488393 0 0
T33 1232938 1232938 0 0
T34 1209096 1209089 0 0
T35 4685072 4685023 0 0
T61 51888 49712 0 0
T62 225224 213200 0 0
T63 12888 12136 0 0
T64 18592 17824 0 0
T65 23920 23352 0 0
T66 12632 11808 0 0
T67 52360 51688 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 539591562 0 0
T4 4424815 345610 0 0
T5 1933595 136383 0 0
T6 1358440 58145 0 0
T10 1959510 208443 0 0
T11 15395 843 0 0
T12 15705 220 0 0
T32 3206020 516616 0 0
T33 880670 1346530 0 0
T34 863640 1349182 0 0
T35 3346480 515223 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 10160 10160 0 0
T1 8 8 0 0
T2 8 8 0 0
T3 8 8 0 0
T61 8 8 0 0
T62 8 8 0 0
T63 8 8 0 0
T64 8 8 0 0
T65 8 8 0 0
T66 8 8 0 0
T67 8 8 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%