Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	118480795	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1270	1270	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	118480795	0	0
T2	1692	32	0	0
T3	879	0	0	0
T4	0	9832	0	0
T5	0	1075	0	0
T61	6486	0	0	0
T62	28153	0	0	0
T63	1611	0	0	0
T64	2324	0	0	0
T65	2990	0	0	0
T66	1579	43	0	0
T67	6545	211	0	0
T68	0	348	0	0
T69	1371	0	0	0
T70	0	335	0	0
T71	0	414	0	0
T73	0	120	0	0
T80	0	456	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	154332	154269	0	0
T2	1692	1625	0	0
T3	879	822	0	0
T61	6486	6214	0	0
T62	28153	26650	0	0
T63	1611	1517	0	0
T64	2324	2228	0	0
T65	2990	2919	0	0
T66	1579	1476	0	0
T67	6545	6461	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	154332	154269	0	0
T2	1692	1625	0	0
T3	879	822	0	0
T61	6486	6214	0	0
T62	28153	26650	0	0
T63	1611	1517	0	0
T64	2324	2228	0	0
T65	2990	2919	0	0
T66	1579	1476	0	0
T67	6545	6461	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	154332	154269	0	0
T2	1692	1625	0	0
T3	879	822	0	0
T61	6486	6214	0	0
T62	28153	26650	0	0
T63	1611	1517	0	0
T64	2324	2228	0	0
T65	2990	2919	0	0
T66	1579	1476	0	0
T67	6545	6461	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270	1270	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	224763057	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1270	1270	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	224763057	0	0
T2	1692	112	0	0
T3	879	0	0	0
T4	0	46249	0	0
T5	0	4943	0	0
T61	6486	0	0	0
T62	28153	0	0	0
T63	1611	0	0	0
T64	2324	0	0	0
T65	2990	0	0	0
T66	1579	40	0	0
T67	6545	208	0	0
T68	0	290	0	0
T69	1371	0	0	0
T70	0	739	0	0
T71	0	350	0	0
T73	0	526	0	0
T80	0	268	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	154332	154269	0	0
T2	1692	1625	0	0
T3	879	822	0	0
T61	6486	6214	0	0
T62	28153	26650	0	0
T63	1611	1517	0	0
T64	2324	2228	0	0
T65	2990	2919	0	0
T66	1579	1476	0	0
T67	6545	6461	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	154332	154269	0	0
T2	1692	1625	0	0
T3	879	822	0	0
T61	6486	6214	0	0
T62	28153	26650	0	0
T63	1611	1517	0	0
T64	2324	2228	0	0
T65	2990	2919	0	0
T66	1579	1476	0	0
T67	6545	6461	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	154332	154269	0	0
T2	1692	1625	0	0
T3	879	822	0	0
T61	6486	6214	0	0
T62	28153	26650	0	0
T63	1611	1517	0	0
T64	2324	2228	0	0
T65	2990	2919	0	0
T66	1579	1476	0	0
T67	6545	6461	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270	1270	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	327142018	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1270	1270	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	327142018	0	0
T1	154332	14830	0	0
T2	1692	162	0	0
T3	879	38	0	0
T61	6486	1284	0	0
T62	28153	2993	0	0
T63	1611	40	0	0
T64	2324	285	0	0
T65	2990	614	0	0
T66	1579	98	0	0
T67	6545	494	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	154332	154269	0	0
T2	1692	1625	0	0
T3	879	822	0	0
T61	6486	6214	0	0
T62	28153	26650	0	0
T63	1611	1517	0	0
T64	2324	2228	0	0
T65	2990	2919	0	0
T66	1579	1476	0	0
T67	6545	6461	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	154332	154269	0	0
T2	1692	1625	0	0
T3	879	822	0	0
T61	6486	6214	0	0
T62	28153	26650	0	0
T63	1611	1517	0	0
T64	2324	2228	0	0
T65	2990	2919	0	0
T66	1579	1476	0	0
T67	6545	6461	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	154332	154269	0	0
T2	1692	1625	0	0
T3	879	822	0	0
T61	6486	6214	0	0
T62	28153	26650	0	0
T63	1611	1517	0	0
T64	2324	2228	0	0
T65	2990	2919	0	0
T66	1579	1476	0	0
T67	6545	6461	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270	1270	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	626084233	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1270	1270	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	626084233	0	0
T1	154332	66175	0	0
T2	1692	370	0	0
T3	879	38	0	0
T61	6486	2204	0	0
T62	28153	2757	0	0
T63	1611	170	0	0
T64	2324	263	0	0
T65	2990	1221	0	0
T66	1579	93	0	0
T67	6545	468	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	154332	154269	0	0
T2	1692	1625	0	0
T3	879	822	0	0
T61	6486	6214	0	0
T62	28153	26650	0	0
T63	1611	1517	0	0
T64	2324	2228	0	0
T65	2990	2919	0	0
T66	1579	1476	0	0
T67	6545	6461	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	154332	154269	0	0
T2	1692	1625	0	0
T3	879	822	0	0
T61	6486	6214	0	0
T62	28153	26650	0	0
T63	1611	1517	0	0
T64	2324	2228	0	0
T65	2990	2919	0	0
T66	1579	1476	0	0
T67	6545	6461	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	154332	154269	0	0
T2	1692	1625	0	0
T3	879	822	0	0
T61	6486	6214	0	0
T62	28153	26650	0	0
T63	1611	1517	0	0
T64	2324	2228	0	0
T65	2990	2919	0	0
T66	1579	1476	0	0
T67	6545	6461	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270	1270	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0