SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.15 | 100.00 | 95.74 | 100.00 | 100.00 | 100.00 | gen_entropy.u_entropy |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.15 | 100.00 | 95.74 | 100.00 | 100.00 | 100.00 | gen_entropy.u_entropy |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.15 | 100.00 | 95.74 | 100.00 | 100.00 | 100.00 | gen_entropy.u_entropy |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.15 | 100.00 | 95.74 | 100.00 | 100.00 | 100.00 | gen_entropy.u_entropy |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.15 | 100.00 | 95.74 | 100.00 | 100.00 | 100.00 | gen_entropy.u_entropy |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.15 | 100.00 | 95.74 | 100.00 | 100.00 | 100.00 | gen_entropy.u_entropy |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.15 | 100.00 | 95.74 | 100.00 | 100.00 | 100.00 | gen_entropy.u_entropy |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.15 | 100.00 | 95.74 | 100.00 | 100.00 | 100.00 | gen_entropy.u_entropy |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.15 | 100.00 | 95.74 | 100.00 | 100.00 | 100.00 | gen_entropy.u_entropy |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.15 | 100.00 | 95.74 | 100.00 | 100.00 | 100.00 | gen_entropy.u_entropy |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.15 | 100.00 | 95.74 | 100.00 | 100.00 | 100.00 | gen_entropy.u_entropy |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.15 | 100.00 | 95.74 | 100.00 | 100.00 | 100.00 | gen_entropy.u_entropy |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.15 | 100.00 | 95.74 | 100.00 | 100.00 | 100.00 | gen_entropy.u_entropy |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.15 | 100.00 | 95.74 | 100.00 | 100.00 | 100.00 | gen_entropy.u_entropy |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.15 | 100.00 | 95.74 | 100.00 | 100.00 | 100.00 | gen_entropy.u_entropy |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.15 | 100.00 | 95.74 | 100.00 | 100.00 | 100.00 | gen_entropy.u_entropy |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.15 | 100.00 | 95.74 | 100.00 | 100.00 | 100.00 | gen_entropy.u_entropy |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.15 | 100.00 | 95.74 | 100.00 | 100.00 | 100.00 | gen_entropy.u_entropy |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.15 | 100.00 | 95.74 | 100.00 | 100.00 | 100.00 | gen_entropy.u_entropy |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.15 | 100.00 | 95.74 | 100.00 | 100.00 | 100.00 | gen_entropy.u_entropy |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.15 | 100.00 | 95.74 | 100.00 | 100.00 | 100.00 | gen_entropy.u_entropy |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.15 | 100.00 | 95.74 | 100.00 | 100.00 | 100.00 | gen_entropy.u_entropy |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.15 | 100.00 | 95.74 | 100.00 | 100.00 | 100.00 | gen_entropy.u_entropy |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.15 | 100.00 | 95.74 | 100.00 | 100.00 | 100.00 | gen_entropy.u_entropy |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.15 | 100.00 | 95.74 | 100.00 | 100.00 | 100.00 | gen_entropy.u_entropy |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 6 | 6 | 100.00 |
Total Bits | 136 | 136 | 100.00 |
Total Bits 0->1 | 68 | 68 | 100.00 |
Total Bits 1->0 | 68 | 68 | 100.00 |
Ports | 6 | 6 | 100.00 |
Port Bits | 136 | 136 | 100.00 |
Port Bits 0->1 | 68 | 68 | 100.00 |
Port Bits 1->0 | 68 | 68 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T10,T12,T13 | Yes | T4,T5,T6 | INPUT |
seed_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
seed_i[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
lfsr_en_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
entropy_i[7:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
state_o[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |