Unified Coverage Report :: Module :: kmac_entropy

Module : kmac_entropy

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.15	100.00	95.74		80.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_entropy.u_entropy	99.15	100.00	95.74		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_entropy.u_entropy

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.15	100.00	95.74		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.29	100.00	95.74	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_lfsrs[0].u_lfsr_chunk	100.00			100.00
gen_lfsrs[10].u_lfsr_chunk	100.00			100.00
gen_lfsrs[11].u_lfsr_chunk	100.00			100.00
gen_lfsrs[12].u_lfsr_chunk	100.00			100.00
gen_lfsrs[13].u_lfsr_chunk	100.00			100.00
gen_lfsrs[14].u_lfsr_chunk	100.00			100.00
gen_lfsrs[15].u_lfsr_chunk	100.00			100.00
gen_lfsrs[16].u_lfsr_chunk	100.00			100.00
gen_lfsrs[17].u_lfsr_chunk	100.00			100.00
gen_lfsrs[18].u_lfsr_chunk	100.00			100.00
gen_lfsrs[19].u_lfsr_chunk	100.00			100.00
gen_lfsrs[1].u_lfsr_chunk	100.00			100.00
gen_lfsrs[20].u_lfsr_chunk	100.00			100.00
gen_lfsrs[21].u_lfsr_chunk	100.00			100.00
gen_lfsrs[22].u_lfsr_chunk	100.00			100.00
gen_lfsrs[23].u_lfsr_chunk	100.00			100.00
gen_lfsrs[24].u_lfsr_chunk	100.00			100.00
gen_lfsrs[2].u_lfsr_chunk	100.00			100.00
gen_lfsrs[3].u_lfsr_chunk	100.00			100.00
gen_lfsrs[4].u_lfsr_chunk	100.00			100.00
gen_lfsrs[5].u_lfsr_chunk	100.00			100.00
gen_lfsrs[6].u_lfsr_chunk	100.00			100.00
gen_lfsrs[7].u_lfsr_chunk	100.00			100.00
gen_lfsrs[8].u_lfsr_chunk	100.00			100.00
gen_lfsrs[9].u_lfsr_chunk	100.00			100.00
u_entropy_configured	100.00	100.00				100.00	100.00
u_hash_count	100.00			100.00
u_seed_idx_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : kmac_entropy

	Line No.	Total	Covered	Percent
TOTAL		1610	1610	100.00
ALWAYS	241	4	4	100.00
ALWAYS	250	4	4	100.00
ALWAYS	259	8	8	100.00
CONT_ASSIGN	270	1	1	100.00
ALWAYS	273	6	6	100.00
ALWAYS	284	8	8	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	304	3	3	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
CONT_ASSIGN	314	1	1	100.00
CONT_ASSIGN	337	1	1	100.00
ALWAYS	340	6	6	100.00
ALWAYS	346	4	4	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	402	1	1	100.00
CONT_ASSIGN	402	1	1	100.00
CONT_ASSIGN	402	1	1	100.00
CONT_ASSIGN	402	1	1	100.00
CONT_ASSIGN	402	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
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CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
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CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
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CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
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CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
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CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
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CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
ALWAYS	467	3	3	100.00
CONT_ASSIGN	477	1	1	100.00
ALWAYS	482	3	3	100.00
CONT_ASSIGN	492	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
ALWAYS	497	6	6	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	526	1	1	100.00
ALWAYS	528	3	3	100.00
CONT_ASSIGN	538	1	1	100.00
ALWAYS	547	3	3	100.00
ALWAYS	552	78	78	100.00
ALWAYS	790	3	3	100.00
CONT_ASSIGN	799	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
241	1	1
242	1	1
243	1	1
244	1	1
			MISSING_ELSE
250	1	1
251	1	1
252	1	1
253	1	1
			MISSING_ELSE
259	1	1
260	1	1
261	1	1
262	1	1
263	1	1
264	1	1
265	1	1
266	1	1
			MISSING_ELSE
270	1	1
273	1	1
274	1	1
275	1	1
276	1	1
277	1	1
278	1	1
			MISSING_ELSE
284	1	1
285	1	1
286	1	1
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
			MISSING_ELSE
295	1	1
304	2	2
305	1	1
308	1	1
311	1	1
314	1	1
337	1	1
340	2	2
341	2	2
342	2	2
			MISSING_ELSE
346	2	2
347	2	2
			MISSING_ELSE
394	1	1
402	5	5
410	5	5
416	640	640
453	1	1
455	800	800
459	1	1
464	1	1
467	1	1
468	1	1
470	1	1
477	1	1
482	1	1
483	1	1
485	1	1
492	1	1
493	1	1
497	1	1
498	1	1
499	1	1
500	1	1
501	1	1
502	1	1
			MISSING_ELSE
507	1	1
525	1	1
526	1	1
528	1	1
529	1	1
531	1	1
538	1	1
547	3	3
552	1	1
553	1	1
556	1	1
557	1	1
559	1	1
562	1	1
570	1	1
571	1	1
574	1	1
578	1	1
582	1	1
585	1	1
588	1	1
591	1	1
593	1	1
595	1	1
598	1	1
600	1	1
602	1	1
604	1	1
608	1	1
611	1	1
621	1	1
626	1	1
631	1	1
633	1	1
635	1	1
644	1	1
645	1	1
647	1	1
648	1	1
650	1	1
652	1	1
654	1	1
656	1	1
659	1	1
662	1	1
664	1	1
670	1	1
673	1	1
675	1	1
677	1	1
679	1	1
680	1	1
682	1	1
683	1	1
685	1	1
686	1	1
687	1	1
			MISSING_ELSE
690	1	1
692	1	1
699	1	1
701	1	1
702	1	1
704	1	1
709	1	1
711	1	1
712	1	1
714	1	1
716	1	1
718	1	1
724	1	1
728	1	1
729	1	1
731	1	1
735	1	1
737	1	1
744	1	1
746	1	1
754	1	1
757	1	1
759	1	1
760	1	1
763	1	1
770	1	1
771	1	1
783	1	1
784	1	1
			MISSING_ELSE
790	1	1
791	1	1
793	1	1
799	1	1

---

Cond Coverage for Module : kmac_entropy

	Total	Covered	Percent
Conditions	188	180	95.74
Logical	188	180	95.74
Non-Logical	0	0
Event	0	0

 LINE       265
 EXPRESSION (timer_enable && timer_pulse && ((|timer_value)))
             ------1-----    -----2-----    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T12,T13,T14
1	1	0	Covered	T4,T6,T10
1	1	1	Covered	T12,T13,T14

 LINE       277
 EXPRESSION (timer_enable && (timer_value == '0))
             ------1-----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T12,T13,T14
1	1	Covered	T4,T5,T6

 LINE       277
 SUB-EXPRESSION (timer_value == '0)
                ---------1---------

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T4,T5,T6

 LINE       288
 EXPRESSION (timer_enable && (prescaler_cnt == '0))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T12,T22
1	1	Covered	T4,T5,T6

 LINE       288
 SUB-EXPRESSION (prescaler_cnt == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T5,T12,T22
1	Covered	T4,T5,T6

 LINE       295
 EXPRESSION (timer_enable && (prescaler_cnt == '0))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T12,T22
1	1	Covered	T4,T5,T6

 LINE       295
 SUB-EXPRESSION (prescaler_cnt == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       311
 EXPRESSION (hash_cnt_clr_i || threshold_hit || entropy_refresh_req_i)
             -------1------    ------2------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T15,T17,T33
0	1	0	Covered	T33,T74,T75
1	0	0	Covered	T17,T33,T76

 LINE       314
 EXPRESSION (hash_progress_q && ((!hash_progress_d)))
             -------1-------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       337
 EXPRESSION (((|hash_threshold_i)) && (hash_threshold_i <= hash_cnt_o))
             ----------1----------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T15,T16,T17
1	1	Covered	T33,T74,T75

 LINE       410
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[0] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T10

 LINE       410
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T10

 LINE       410
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[1] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T10

 LINE       410
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T10

 LINE       410
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[2] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T10

 LINE       410
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T10

 LINE       410
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[3] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T10

 LINE       410
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T10

 LINE       410
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[4] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T10

 LINE       410
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T10

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       464
 EXPRESSION (aux_update ? lfsr_data_permuted[(kmac_pkg::EntropyLfsrW - 1)] : aux_rand_q)
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       477
 EXPRESSION (aux_update ? lfsr_data_permuted[(kmac_pkg::EntropyLfsrW - 2)-:4] : ({1'b0, lfsr_en_rand_q[3:1]}))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       525
 EXPRESSION (entropy_req | entropy_req_hold_q)
             -----1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T11,T77,T78
1	0	Covered	T5,T12,T22

 LINE       526
 EXPRESSION ((entropy_req_hold_q | entropy_req) & ((~entropy_ack_i)))
             -----------------1----------------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T12,T22
1	1	Covered	T5,T12,T22

 LINE       526
 SUB-EXPRESSION (entropy_req_hold_q | entropy_req)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T12,T22
1	0	Covered	T11,T77,T78

 LINE       538
 EXPRESSION (hash_count_error | seed_idx_count_error)
             --------1-------   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       635
 EXPRESSION (rand_consumed_i && ((fast_process_i && in_keyblock_i) || ((!fast_process_i))))
             -------1-------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       635
 SUB-EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
                 ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       635
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       654
 EXPRESSION ((mode_q == EntropyModeEdn) && (entropy_refresh_req_i || threshold_hit_q))
             -------------1------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T75,T79
1	0	Covered	T5,T12,T22
1	1	Covered	T15,T33,T76

 LINE       654
 SUB-EXPRESSION (mode_q == EntropyModeEdn)
                -------------1------------

-1-	Status	Tests
0	Covered	T4,T6,T10
1	Covered	T5,T12,T22

 LINE       654
 SUB-EXPRESSION (entropy_refresh_req_i || threshold_hit_q)
                 ----------1----------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T33,T74,T75
1	0	Covered	T15,T17,T33

 LINE       675
 EXPRESSION (timer_expired && non_zero_wait_timer_limit)
             ------1------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T5,T12,T22
1	1	Covered	T77,T78,T80

 LINE       685
 EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
             ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T22,T23
0	1	Covered	T5,T12,T25
1	0	Covered	T35,T81,T82

 LINE       685
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T22,T23
1	1	Covered	T35,T81,T82

 LINE       692
 EXPRESSION (rand_consumed_i && ((fast_process_i && in_keyblock_i) || ((!fast_process_i))))
             -------1-------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T12,T25
1	0	Covered	T33,T83,T34
1	1	Covered	T33,T34,T35

 LINE       692
 SUB-EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
                 ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T22,T23
0	1	Covered	T5,T12,T25
1	0	Covered	T35,T81,T82

 LINE       692
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T22,T23
1	1	Covered	T35,T81,T82

 LINE       757
 EXPRESSION (rand_consumed_i & ((fast_process_i & in_keyblock_i) | ((~fast_process_i))))
             -------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T84,T85,T77
1	0	Not Covered
1	1	Not Covered

 LINE       757
 SUB-EXPRESSION ((fast_process_i & in_keyblock_i) | ((~fast_process_i)))
                 ----------------1---------------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T84,T85,T86
0	1	Covered	T84,T85,T77
1	0	Not Covered

 LINE       757
 SUB-EXPRESSION (fast_process_i & in_keyblock_i)
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T84,T85,T86
1	1	Not Covered

 LINE       799
 EXPRESSION ((st != StRandReset) ? MuBi4True : MuBi4False)
             ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       799
 SUB-EXPRESSION (st != StRandReset)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

---

FSM Coverage for Module : kmac_entropy

Summary for FSM :: st

	Total	Covered	Percent
States	9	9	100.00	(Not included in score)
Transitions	20	16	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StRandEdn	608	Covered	T1
StRandErr	735	Covered	T1
StRandErrIncorrectMode	617	Covered	T1
StRandErrWaitExpired	677	Covered	T1
StRandGenerate	648	Covered	T1
StRandReady	652	Covered	T1
StRandReset	621	Covered	T1
StSwSeedWait	604	Covered	T1
StTerminalError	784	Covered	T1

transitions	Line No.	Covered	Tests
StRandEdn->StRandErrWaitExpired	677	Covered	T1
StRandEdn->StRandGenerate	683	Covered	T1
StRandEdn->StTerminalError	784	Covered	T1
StRandErr->StRandReset	760	Covered	T1
StRandErr->StTerminalError	784	Not Covered
StRandErrIncorrectMode->StRandErr	744	Covered	T1
StRandErrIncorrectMode->StTerminalError	784	Not Covered
StRandErrWaitExpired->StRandErr	735	Covered	T1
StRandErrWaitExpired->StTerminalError	784	Not Covered
StRandGenerate->StRandReady	731	Covered	T1
StRandGenerate->StTerminalError	784	Covered	T1
StRandReady->StRandEdn	656	Covered	T1
StRandReady->StRandGenerate	648	Covered	T1
StRandReady->StTerminalError	784	Covered	T1
StRandReset->StRandEdn	608	Covered	T1
StRandReset->StRandErrIncorrectMode	617	Covered	T1
StRandReset->StSwSeedWait	604	Covered	T1
StRandReset->StTerminalError	784	Covered	T1
StSwSeedWait->StRandGenerate	712	Covered	T1
StSwSeedWait->StTerminalError	784	Not Covered

---

Branch Coverage for Module : kmac_entropy

	Line No.	Total	Covered	Percent
Branches		84	84	100.00
TERNARY	464	2	2	100.00
TERNARY	477	2	2	100.00
TERNARY	799	2	2	100.00
TERNARY	410	2	2	100.00
TERNARY	410	2	2	100.00
TERNARY	410	2	2	100.00
TERNARY	410	2	2	100.00
TERNARY	410	2	2	100.00
IF	241	3	3	100.00
IF	250	3	3	100.00
IF	259	5	5	100.00
IF	273	4	4	100.00
IF	284	5	5	100.00
IF	304	2	2	100.00
IF	340	4	4	100.00
IF	346	3	3	100.00
IF	467	2	2	100.00
IF	482	2	2	100.00
IF	497	4	4	100.00
IF	528	2	2	100.00
IF	547	2	2	100.00
CASE	593	23	23	100.00
IF	783	2	2	100.00
IF	790	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	464	(aux_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	477	(aux_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	799	((st != StRandReset)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	410	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	410	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	410	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	410	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	410	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	241	if ((!rst_ni))
-2-:	243	if (timer_update)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T5,T12,T22
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	250	if ((!rst_ni))
-2-:	252	if (timer_update)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T5,T12,T22
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	259	if ((!rst_ni))
-2-:	261	if (timer_update)
-3-:	263	if (timer_expired)
-4-:	265	if (((timer_enable && timer_pulse) && (|timer_value)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Covered	T5,T12,T22
0	0	1	-	Covered	T4,T5,T6
0	0	0	1	Covered	T12,T13,T14
0	0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	273	if ((!rst_ni))
-2-:	275	if (timer_update)
-3-:	277	if ((timer_enable && (timer_value == '0)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T5,T12,T22
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	284	if ((!rst_ni))
-2-:	286	if (timer_update)
-3-:	288	if ((timer_enable && (prescaler_cnt == '0)))
-4-:	290	if (timer_enable)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Covered	T5,T12,T22
0	0	1	-	Covered	T4,T5,T6
0	0	0	1	Covered	T5,T12,T22
0	0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	304	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	340	if ((!rst_ni))
-2-:	341	if (threshold_hit_clr)
-3-:	342	if (threshold_hit)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T15,T33,T76
0	0	1	Covered	T33,T74,T75
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	346	if ((!rst_ni))
-2-:	347	if (mode_latch)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	467	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	482	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	497	if ((!rst_ni))
-2-:	499	if (rand_valid_set)
-3-:	501	if (rand_valid_clear)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	528	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	547	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	593	case (st)
-2-:	595	if (entropy_ready_i)
-3-:	602	case (mode_i)
-4-:	635	if ((rand_consumed_i && ((fast_process_i && in_keyblock_i) || (!fast_process_i))))
-5-:	647	if (ready_phase_q)
-6-:	654	if (((mode_q == EntropyModeEdn) && (entropy_refresh_req_i || threshold_hit_q)))
-7-:	675	if ((timer_expired && non_zero_wait_timer_limit))
-8-:	679	if (entropy_ack_i)
-9-:	682	if (lfsr_seed_done)
-10-:	685	if (((fast_process_i && in_keyblock_i) || (!fast_process_i)))
-11-:	692	if ((rand_consumed_i && ((fast_process_i && in_keyblock_i) || (!fast_process_i))))
-12-:	711	if (lfsr_seed_done)
-13-:	759	if (err_processed_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StRandReset	1	EntropyModeSw	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T10
StRandReset	1	EntropyModeEdn	-	-	-	-	-	-	-	-	-	-	Covered	T5,T12,T22
StRandReset	1	default	-	-	-	-	-	-	-	-	-	-	Covered	T84,T85,T86
StRandReset	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StRandReady	-	-	1	1	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StRandReady	-	-	1	0	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StRandReady	-	-	0	-	1	-	-	-	-	-	-	-	Covered	T15,T33,T76
StRandReady	-	-	0	-	0	-	-	-	-	-	-	-	Covered	T4,T5,T6
StRandEdn	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T77,T78,T80
StRandEdn	-	-	-	-	-	0	1	1	1	-	-	-	Covered	T5,T12,T25
StRandEdn	-	-	-	-	-	0	1	1	0	-	-	-	Covered	T12,T22,T23
StRandEdn	-	-	-	-	-	0	1	0	-	-	-	-	Covered	T5,T12,T22
StRandEdn	-	-	-	-	-	0	0	-	-	1	-	-	Covered	T33,T34,T35
StRandEdn	-	-	-	-	-	0	0	-	-	0	-	-	Covered	T5,T12,T22
StSwSeedWait	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T4,T6,T10
StSwSeedWait	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T4,T6,T10
StRandGenerate	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StRandErrWaitExpired	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T77,T78,T80
StRandErrIncorrectMode	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T84,T85,T86
StRandErr	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T84,T85,T77
StRandErr	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T84,T85,T77
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	783	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T7
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	790	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Module : kmac_entropy

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	9	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	9	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ChunkSizeEntropyLfsrMatchesEdn	1049	1049	0	0
ChunkSizeEntropyLfsrMatchesSw	1049	1049	0	0
ConsumeNotAssertWhenNotValid_M	2147483647	157559648	0	0
EntropyLfsrWDivisble	1049	1049	0	0
ModeKnown_A	2147483647	2147483647	0	0
RandStKnown_A	2147483647	2147483647	0	0
p_perm_check.PermutationCheck_A	1049	1049	0	0
p_perm_fwd_check.PermutationCheck_A	1049	1049	0	0
u_state_regs_A	2147483647	2147483647	0	0

ChunkSizeEntropyLfsrMatchesEdn

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049	1049	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T30	1	1	0	0

ChunkSizeEntropyLfsrMatchesSw

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049	1049	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T30	1	1	0	0

ConsumeNotAssertWhenNotValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	157559648	0	0
T4	108871	14160	0	0
T5	101041	144720	0	0
T6	218586	31872	0	0
T10	22515	912	0	0
T12	186166	113088	0	0
T22	64882	0	0	0
T23	262412	631056	0	0
T24	478610	262176	0	0
T25	10769	1488	0	0
T26	0	265248	0	0
T30	129182	5088	0	0

EntropyLfsrWDivisble

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049	1049	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T30	1	1	0	0

ModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	108871	108775	0	0
T5	101041	101031	0	0
T6	218586	218536	0	0
T10	22515	22364	0	0
T12	186166	186107	0	0
T22	64882	64803	0	0
T23	262412	262411	0	0
T24	478610	478603	0	0
T25	10769	10684	0	0
T30	129182	129100	0	0

RandStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	108871	108775	0	0
T5	101041	101031	0	0
T6	218586	218536	0	0
T10	22515	22364	0	0
T12	186166	186107	0	0
T22	64882	64803	0	0
T23	262412	262411	0	0
T24	478610	478603	0	0
T25	10769	10684	0	0
T30	129182	129100	0	0

p_perm_check.PermutationCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049	1049	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T30	1	1	0	0

p_perm_fwd_check.PermutationCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049	1049	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T30	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	108871	108775	0	0
T5	101041	101031	0	0
T6	218586	218536	0	0
T10	22515	22364	0	0
T12	186166	186107	0	0
T22	64882	64803	0	0
T23	262412	262411	0	0
T24	478610	478603	0	0
T25	10769	10684	0	0
T30	129182	129100	0	0

Line Coverage for Instance : tb.dut.gen_entropy.u_entropy

	Line No.	Total	Covered	Percent
TOTAL		1610	1610	100.00
ALWAYS	241	4	4	100.00
ALWAYS	250	4	4	100.00
ALWAYS	259	8	8	100.00
CONT_ASSIGN	270	1	1	100.00
ALWAYS	273	6	6	100.00
ALWAYS	284	8	8	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	304	3	3	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
CONT_ASSIGN	314	1	1	100.00
CONT_ASSIGN	337	1	1	100.00
ALWAYS	340	6	6	100.00
ALWAYS	346	4	4	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	402	1	1	100.00
CONT_ASSIGN	402	1	1	100.00
CONT_ASSIGN	402	1	1	100.00
CONT_ASSIGN	402	1	1	100.00
CONT_ASSIGN	402	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
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CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
ALWAYS	467	3	3	100.00
CONT_ASSIGN	477	1	1	100.00
ALWAYS	482	3	3	100.00
CONT_ASSIGN	492	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
ALWAYS	497	6	6	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	526	1	1	100.00
ALWAYS	528	3	3	100.00
CONT_ASSIGN	538	1	1	100.00
ALWAYS	547	3	3	100.00
ALWAYS	552	78	78	100.00
ALWAYS	790	3	3	100.00
CONT_ASSIGN	799	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
241	1	1
242	1	1
243	1	1
244	1	1
			MISSING_ELSE
250	1	1
251	1	1
252	1	1
253	1	1
			MISSING_ELSE
259	1	1
260	1	1
261	1	1
262	1	1
263	1	1
264	1	1
265	1	1
266	1	1
			MISSING_ELSE
270	1	1
273	1	1
274	1	1
275	1	1
276	1	1
277	1	1
278	1	1
			MISSING_ELSE
284	1	1
285	1	1
286	1	1
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
			MISSING_ELSE
295	1	1
304	2	2
305	1	1
308	1	1
311	1	1
314	1	1
337	1	1
340	2	2
341	2	2
342	2	2
			MISSING_ELSE
346	2	2
347	2	2
			MISSING_ELSE
394	1	1
402	5	5
410	5	5
416	640	640
453	1	1
455	800	800
459	1	1
464	1	1
467	1	1
468	1	1
470	1	1
477	1	1
482	1	1
483	1	1
485	1	1
492	1	1
493	1	1
497	1	1
498	1	1
499	1	1
500	1	1
501	1	1
502	1	1
			MISSING_ELSE
507	1	1
525	1	1
526	1	1
528	1	1
529	1	1
531	1	1
538	1	1
547	3	3
552	1	1
553	1	1
556	1	1
557	1	1
559	1	1
562	1	1
570	1	1
571	1	1
574	1	1
578	1	1
582	1	1
585	1	1
588	1	1
591	1	1
593	1	1
595	1	1
598	1	1
600	1	1
602	1	1
604	1	1
608	1	1
611	1	1
621	1	1
626	1	1
631	1	1
633	1	1
635	1	1
644	1	1
645	1	1
647	1	1
648	1	1
650	1	1
652	1	1
654	1	1
656	1	1
659	1	1
662	1	1
664	1	1
670	1	1
673	1	1
675	1	1
677	1	1
679	1	1
680	1	1
682	1	1
683	1	1
685	1	1
686	1	1
687	1	1
			MISSING_ELSE
690	1	1
692	1	1
699	1	1
701	1	1
702	1	1
704	1	1
709	1	1
711	1	1
712	1	1
714	1	1
716	1	1
718	1	1
724	1	1
728	1	1
729	1	1
731	1	1
735	1	1
737	1	1
744	1	1
746	1	1
754	1	1
757	1	1
759	1	1
760	1	1
763	1	1
770	1	1
771	1	1
783	1	1
784	1	1
			MISSING_ELSE
790	1	1
791	1	1
793	1	1
799	1	1

---

Cond Coverage for Instance : tb.dut.gen_entropy.u_entropy

	Total	Covered	Percent
Conditions	188	180	95.74
Logical	188	180	95.74
Non-Logical	0	0
Event	0	0

 LINE       265
 EXPRESSION (timer_enable && timer_pulse && ((|timer_value)))
             ------1-----    -----2-----    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T12,T13,T14
1	1	0	Covered	T4,T6,T10
1	1	1	Covered	T12,T13,T14

 LINE       277
 EXPRESSION (timer_enable && (timer_value == '0))
             ------1-----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T12,T13,T14
1	1	Covered	T4,T5,T6

 LINE       277
 SUB-EXPRESSION (timer_value == '0)
                ---------1---------

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T4,T5,T6

 LINE       288
 EXPRESSION (timer_enable && (prescaler_cnt == '0))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T12,T22
1	1	Covered	T4,T5,T6

 LINE       288
 SUB-EXPRESSION (prescaler_cnt == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T5,T12,T22
1	Covered	T4,T5,T6

 LINE       295
 EXPRESSION (timer_enable && (prescaler_cnt == '0))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T12,T22
1	1	Covered	T4,T5,T6

 LINE       295
 SUB-EXPRESSION (prescaler_cnt == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       311
 EXPRESSION (hash_cnt_clr_i || threshold_hit || entropy_refresh_req_i)
             -------1------    ------2------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T15,T17,T33
0	1	0	Covered	T33,T74,T75
1	0	0	Covered	T17,T33,T76

 LINE       314
 EXPRESSION (hash_progress_q && ((!hash_progress_d)))
             -------1-------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       337
 EXPRESSION (((|hash_threshold_i)) && (hash_threshold_i <= hash_cnt_o))
             ----------1----------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T15,T16,T17
1	1	Covered	T33,T74,T75

 LINE       410
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[0] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T10

 LINE       410
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T10

 LINE       410
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[1] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T10

 LINE       410
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T10

 LINE       410
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[2] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T10

 LINE       410
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T10

 LINE       410
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[3] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T10

 LINE       410
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T10

 LINE       410
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i[4] : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T10

 LINE       410
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T10

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       440
 EXPRESSION (lfsr_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       464
 EXPRESSION (aux_update ? lfsr_data_permuted[(kmac_pkg::EntropyLfsrW - 1)] : aux_rand_q)
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       477
 EXPRESSION (aux_update ? lfsr_data_permuted[(kmac_pkg::EntropyLfsrW - 2)-:4] : ({1'b0, lfsr_en_rand_q[3:1]}))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       525
 EXPRESSION (entropy_req | entropy_req_hold_q)
             -----1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T11,T77,T78
1	0	Covered	T5,T12,T22

 LINE       526
 EXPRESSION ((entropy_req_hold_q | entropy_req) & ((~entropy_ack_i)))
             -----------------1----------------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T12,T22
1	1	Covered	T5,T12,T22

 LINE       526
 SUB-EXPRESSION (entropy_req_hold_q | entropy_req)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T12,T22
1	0	Covered	T11,T77,T78

 LINE       538
 EXPRESSION (hash_count_error | seed_idx_count_error)
             --------1-------   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       635
 EXPRESSION (rand_consumed_i && ((fast_process_i && in_keyblock_i) || ((!fast_process_i))))
             -------1-------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       635
 SUB-EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
                 ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       635
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       654
 EXPRESSION ((mode_q == EntropyModeEdn) && (entropy_refresh_req_i || threshold_hit_q))
             -------------1------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T75,T79
1	0	Covered	T5,T12,T22
1	1	Covered	T15,T33,T76

 LINE       654
 SUB-EXPRESSION (mode_q == EntropyModeEdn)
                -------------1------------

-1-	Status	Tests
0	Covered	T4,T6,T10
1	Covered	T5,T12,T22

 LINE       654
 SUB-EXPRESSION (entropy_refresh_req_i || threshold_hit_q)
                 ----------1----------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T33,T74,T75
1	0	Covered	T15,T17,T33

 LINE       675
 EXPRESSION (timer_expired && non_zero_wait_timer_limit)
             ------1------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T5,T12,T22
1	1	Covered	T77,T78,T80

 LINE       685
 EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
             ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T22,T23
0	1	Covered	T5,T12,T25
1	0	Covered	T35,T81,T82

 LINE       685
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T22,T23
1	1	Covered	T35,T81,T82

 LINE       692
 EXPRESSION (rand_consumed_i && ((fast_process_i && in_keyblock_i) || ((!fast_process_i))))
             -------1-------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T12,T25
1	0	Covered	T33,T83,T34
1	1	Covered	T33,T34,T35

 LINE       692
 SUB-EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
                 ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T22,T23
0	1	Covered	T5,T12,T25
1	0	Covered	T35,T81,T82

 LINE       692
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T22,T23
1	1	Covered	T35,T81,T82

 LINE       757
 EXPRESSION (rand_consumed_i & ((fast_process_i & in_keyblock_i) | ((~fast_process_i))))
             -------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T84,T85,T77
1	0	Not Covered
1	1	Not Covered

 LINE       757
 SUB-EXPRESSION ((fast_process_i & in_keyblock_i) | ((~fast_process_i)))
                 ----------------1---------------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T84,T85,T86
0	1	Covered	T84,T85,T77
1	0	Not Covered

 LINE       757
 SUB-EXPRESSION (fast_process_i & in_keyblock_i)
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T84,T85,T86
1	1	Not Covered

 LINE       799
 EXPRESSION ((st != StRandReset) ? MuBi4True : MuBi4False)
             ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       799
 SUB-EXPRESSION (st != StRandReset)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

---

FSM Coverage for Instance : tb.dut.gen_entropy.u_entropy

Summary for FSM :: st

	Total	Covered	Percent
States	9	9	100.00	(Not included in score)
Transitions	16	16	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StRandEdn	608	Covered	T1
StRandErr	735	Covered	T1
StRandErrIncorrectMode	617	Covered	T1
StRandErrWaitExpired	677	Covered	T1
StRandGenerate	648	Covered	T1
StRandReady	652	Covered	T1
StRandReset	621	Covered	T1
StSwSeedWait	604	Covered	T1
StTerminalError	784	Covered	T1

transitions	Line No.	Covered	Tests	Exclude Annotation
StRandEdn->StRandErrWaitExpired	677	Covered	T1
StRandEdn->StRandGenerate	683	Covered	T1
StRandEdn->StTerminalError	784	Covered	T1
StRandErr->StRandReset	760	Covered	T1
StRandErr->StTerminalError	784	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StRandErrIncorrectMode->StRandErr	744	Covered	T1
StRandErrIncorrectMode->StTerminalError	784	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StRandErrWaitExpired->StRandErr	735	Covered	T1
StRandErrWaitExpired->StTerminalError	784	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StRandGenerate->StRandReady	731	Covered	T1
StRandGenerate->StTerminalError	784	Covered	T1
StRandReady->StRandEdn	656	Covered	T1
StRandReady->StRandGenerate	648	Covered	T1
StRandReady->StTerminalError	784	Covered	T1
StRandReset->StRandEdn	608	Covered	T1
StRandReset->StRandErrIncorrectMode	617	Covered	T1
StRandReset->StSwSeedWait	604	Covered	T1
StRandReset->StTerminalError	784	Covered	T1
StSwSeedWait->StRandGenerate	712	Covered	T1
StSwSeedWait->StTerminalError	784	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.

---

Branch Coverage for Instance : tb.dut.gen_entropy.u_entropy

	Line No.	Total	Covered	Percent
Branches		84	84	100.00
TERNARY	464	2	2	100.00
TERNARY	477	2	2	100.00
TERNARY	799	2	2	100.00
TERNARY	410	2	2	100.00
TERNARY	410	2	2	100.00
TERNARY	410	2	2	100.00
TERNARY	410	2	2	100.00
TERNARY	410	2	2	100.00
IF	241	3	3	100.00
IF	250	3	3	100.00
IF	259	5	5	100.00
IF	273	4	4	100.00
IF	284	5	5	100.00
IF	304	2	2	100.00
IF	340	4	4	100.00
IF	346	3	3	100.00
IF	467	2	2	100.00
IF	482	2	2	100.00
IF	497	4	4	100.00
IF	528	2	2	100.00
IF	547	2	2	100.00
CASE	593	23	23	100.00
IF	783	2	2	100.00
IF	790	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	464	(aux_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	477	(aux_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	799	((st != StRandReset)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	410	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	410	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	410	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	410	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	410	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	241	if ((!rst_ni))
-2-:	243	if (timer_update)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T5,T12,T22
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	250	if ((!rst_ni))
-2-:	252	if (timer_update)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T5,T12,T22
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	259	if ((!rst_ni))
-2-:	261	if (timer_update)
-3-:	263	if (timer_expired)
-4-:	265	if (((timer_enable && timer_pulse) && (|timer_value)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Covered	T5,T12,T22
0	0	1	-	Covered	T4,T5,T6
0	0	0	1	Covered	T12,T13,T14
0	0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	273	if ((!rst_ni))
-2-:	275	if (timer_update)
-3-:	277	if ((timer_enable && (timer_value == '0)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T5,T12,T22
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	284	if ((!rst_ni))
-2-:	286	if (timer_update)
-3-:	288	if ((timer_enable && (prescaler_cnt == '0)))
-4-:	290	if (timer_enable)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Covered	T5,T12,T22
0	0	1	-	Covered	T4,T5,T6
0	0	0	1	Covered	T5,T12,T22
0	0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	304	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	340	if ((!rst_ni))
-2-:	341	if (threshold_hit_clr)
-3-:	342	if (threshold_hit)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T15,T33,T76
0	0	1	Covered	T33,T74,T75
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	346	if ((!rst_ni))
-2-:	347	if (mode_latch)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	467	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	482	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	497	if ((!rst_ni))
-2-:	499	if (rand_valid_set)
-3-:	501	if (rand_valid_clear)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	528	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	547	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	593	case (st)
-2-:	595	if (entropy_ready_i)
-3-:	602	case (mode_i)
-4-:	635	if ((rand_consumed_i && ((fast_process_i && in_keyblock_i) || (!fast_process_i))))
-5-:	647	if (ready_phase_q)
-6-:	654	if (((mode_q == EntropyModeEdn) && (entropy_refresh_req_i || threshold_hit_q)))
-7-:	675	if ((timer_expired && non_zero_wait_timer_limit))
-8-:	679	if (entropy_ack_i)
-9-:	682	if (lfsr_seed_done)
-10-:	685	if (((fast_process_i && in_keyblock_i) || (!fast_process_i)))
-11-:	692	if ((rand_consumed_i && ((fast_process_i && in_keyblock_i) || (!fast_process_i))))
-12-:	711	if (lfsr_seed_done)
-13-:	759	if (err_processed_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StRandReset	1	EntropyModeSw	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T10
StRandReset	1	EntropyModeEdn	-	-	-	-	-	-	-	-	-	-	Covered	T5,T12,T22
StRandReset	1	default	-	-	-	-	-	-	-	-	-	-	Covered	T84,T85,T86
StRandReset	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StRandReady	-	-	1	1	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StRandReady	-	-	1	0	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StRandReady	-	-	0	-	1	-	-	-	-	-	-	-	Covered	T15,T33,T76
StRandReady	-	-	0	-	0	-	-	-	-	-	-	-	Covered	T4,T5,T6
StRandEdn	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T77,T78,T80
StRandEdn	-	-	-	-	-	0	1	1	1	-	-	-	Covered	T5,T12,T25
StRandEdn	-	-	-	-	-	0	1	1	0	-	-	-	Covered	T12,T22,T23
StRandEdn	-	-	-	-	-	0	1	0	-	-	-	-	Covered	T5,T12,T22
StRandEdn	-	-	-	-	-	0	0	-	-	1	-	-	Covered	T33,T34,T35
StRandEdn	-	-	-	-	-	0	0	-	-	0	-	-	Covered	T5,T12,T22
StSwSeedWait	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T4,T6,T10
StSwSeedWait	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T4,T6,T10
StRandGenerate	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StRandErrWaitExpired	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T77,T78,T80
StRandErrIncorrectMode	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T84,T85,T86
StRandErr	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T84,T85,T77
StRandErr	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T84,T85,T77
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	783	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T7
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	790	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.gen_entropy.u_entropy

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	9	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	9	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ChunkSizeEntropyLfsrMatchesEdn	1049	1049	0	0
ChunkSizeEntropyLfsrMatchesSw	1049	1049	0	0
ConsumeNotAssertWhenNotValid_M	2147483647	157559648	0	0
EntropyLfsrWDivisble	1049	1049	0	0
ModeKnown_A	2147483647	2147483647	0	0
RandStKnown_A	2147483647	2147483647	0	0
p_perm_check.PermutationCheck_A	1049	1049	0	0
p_perm_fwd_check.PermutationCheck_A	1049	1049	0	0
u_state_regs_A	2147483647	2147483647	0	0

ChunkSizeEntropyLfsrMatchesEdn

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049	1049	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T30	1	1	0	0

ChunkSizeEntropyLfsrMatchesSw

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049	1049	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T30	1	1	0	0

ConsumeNotAssertWhenNotValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	157559648	0	0
T4	108871	14160	0	0
T5	101041	144720	0	0
T6	218586	31872	0	0
T10	22515	912	0	0
T12	186166	113088	0	0
T22	64882	0	0	0
T23	262412	631056	0	0
T24	478610	262176	0	0
T25	10769	1488	0	0
T26	0	265248	0	0
T30	129182	5088	0	0

EntropyLfsrWDivisble

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049	1049	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T30	1	1	0	0

ModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	108871	108775	0	0
T5	101041	101031	0	0
T6	218586	218536	0	0
T10	22515	22364	0	0
T12	186166	186107	0	0
T22	64882	64803	0	0
T23	262412	262411	0	0
T24	478610	478603	0	0
T25	10769	10684	0	0
T30	129182	129100	0	0

RandStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	108871	108775	0	0
T5	101041	101031	0	0
T6	218586	218536	0	0
T10	22515	22364	0	0
T12	186166	186107	0	0
T22	64882	64803	0	0
T23	262412	262411	0	0
T24	478610	478603	0	0
T25	10769	10684	0	0
T30	129182	129100	0	0

p_perm_check.PermutationCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049	1049	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T30	1	1	0	0

p_perm_fwd_check.PermutationCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049	1049	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T30	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	108871	108775	0	0
T5	101041	101031	0	0
T6	218586	218536	0	0
T10	22515	22364	0	0
T12	186166	186107	0	0
T22	64882	64803	0	0
T23	262412	262411	0	0
T24	478610	478603	0	0
T25	10769	10684	0	0
T30	129182	129100	0	0