Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1653313	0	0
entropy_period_rd_A	2147483647	3653	0	0
intr_enable_rd_A	2147483647	4617	0	0
prefix_0_rd_A	2147483647	3652	0	0
prefix_10_rd_A	2147483647	3368	0	0
prefix_1_rd_A	2147483647	3464	0	0
prefix_2_rd_A	2147483647	3533	0	0
prefix_3_rd_A	2147483647	3554	0	0
prefix_4_rd_A	2147483647	3430	0	0
prefix_5_rd_A	2147483647	3627	0	0
prefix_6_rd_A	2147483647	3573	0	0
prefix_7_rd_A	2147483647	3752	0	0
prefix_8_rd_A	2147483647	3269	0	0
prefix_9_rd_A	2147483647	3686	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1653313	0	0
T53	7504	177	0	0
T54	1530	91	0	0
T55	2557	144	0	0
T56	2772	16	0	0
T57	0	99	0	0
T58	0	226	0	0
T59	0	110	0	0
T60	0	22	0	0
T63	3341	0	0	0
T64	6262	0	0	0
T65	2460	0	0	0
T66	1632	0	0	0
T67	9194	3	0	0
T68	2469	0	0	0
T110	0	3	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3653	0	0
T2	5040	12	0	0
T3	10776	0	0	0
T47	1005	0	0	0
T48	3656	0	0	0
T49	10302	0	0	0
T50	15318	0	0	0
T51	1554	0	0	0
T52	10422	24	0	0
T53	7504	0	0	0
T54	1530	0	0	0
T61	0	6	0	0
T63	0	4	0	0
T64	0	48	0	0
T93	0	25	0	0
T95	0	26	0	0
T112	0	144	0	0
T133	0	4	0	0
T134	0	131	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4617	0	0
T2	5040	9	0	0
T3	10776	0	0	0
T47	1005	0	0	0
T48	3656	0	0	0
T49	10302	0	0	0
T50	15318	0	0	0
T51	1554	0	0	0
T52	10422	34	0	0
T53	7504	0	0	0
T54	1530	0	0	0
T63	0	12	0	0
T64	0	47	0	0
T93	0	13	0	0
T95	0	29	0	0
T112	0	110	0	0
T132	0	76	0	0
T133	0	12	0	0
T134	0	236	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3652	0	0
T2	5040	11	0	0
T3	10776	0	0	0
T47	1005	0	0	0
T48	3656	0	0	0
T49	10302	0	0	0
T50	15318	0	0	0
T51	1554	0	0	0
T52	10422	25	0	0
T53	7504	0	0	0
T54	1530	0	0	0
T61	0	7	0	0
T63	0	8	0	0
T64	0	17	0	0
T69	0	1	0	0
T93	0	7	0	0
T112	0	64	0	0
T133	0	7	0	0
T134	0	248	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3368	0	0
T2	5040	1	0	0
T3	10776	0	0	0
T47	1005	0	0	0
T48	3656	0	0	0
T49	10302	0	0	0
T50	15318	0	0	0
T51	1554	0	0	0
T52	10422	0	0	0
T53	7504	0	0	0
T54	1530	0	0	0
T61	0	13	0	0
T63	0	7	0	0
T64	0	20	0	0
T68	0	5	0	0
T69	0	3	0	0
T93	0	22	0	0
T112	0	76	0	0
T133	0	18	0	0
T134	0	245	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3464	0	0
T2	5040	2	0	0
T3	10776	0	0	0
T47	1005	0	0	0
T48	3656	0	0	0
T49	10302	0	0	0
T50	15318	0	0	0
T51	1554	0	0	0
T52	10422	24	0	0
T53	7504	0	0	0
T54	1530	0	0	0
T61	0	2	0	0
T63	0	11	0	0
T64	0	23	0	0
T68	0	10	0	0
T93	0	18	0	0
T112	0	64	0	0
T133	0	14	0	0
T134	0	208	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3533	0	0
T2	5040	4	0	0
T3	10776	0	0	0
T47	1005	0	0	0
T48	3656	0	0	0
T49	10302	0	0	0
T50	15318	0	0	0
T51	1554	0	0	0
T52	10422	11	0	0
T53	7504	0	0	0
T54	1530	0	0	0
T61	0	13	0	0
T63	0	6	0	0
T64	0	24	0	0
T69	0	8	0	0
T93	0	8	0	0
T112	0	67	0	0
T133	0	7	0	0
T134	0	218	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3554	0	0
T2	5040	11	0	0
T3	10776	0	0	0
T47	1005	0	0	0
T48	3656	0	0	0
T49	10302	0	0	0
T50	15318	0	0	0
T51	1554	0	0	0
T52	10422	20	0	0
T53	7504	0	0	0
T54	1530	0	0	0
T61	0	13	0	0
T63	0	7	0	0
T64	0	30	0	0
T68	0	8	0	0
T93	0	14	0	0
T112	0	67	0	0
T133	0	21	0	0
T134	0	229	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3430	0	0
T2	5040	6	0	0
T3	10776	0	0	0
T47	1005	0	0	0
T48	3656	0	0	0
T49	10302	0	0	0
T50	15318	0	0	0
T51	1554	0	0	0
T52	10422	47	0	0
T53	7504	0	0	0
T54	1530	0	0	0
T63	0	8	0	0
T64	0	23	0	0
T68	0	2	0	0
T69	0	1	0	0
T93	0	19	0	0
T112	0	80	0	0
T133	0	25	0	0
T134	0	232	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3627	0	0
T2	5040	5	0	0
T3	10776	0	0	0
T47	1005	0	0	0
T48	3656	0	0	0
T49	10302	0	0	0
T50	15318	0	0	0
T51	1554	0	0	0
T52	10422	45	0	0
T53	7504	0	0	0
T54	1530	0	0	0
T61	0	2	0	0
T63	0	9	0	0
T64	0	23	0	0
T68	0	6	0	0
T93	0	14	0	0
T112	0	81	0	0
T133	0	19	0	0
T134	0	231	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3573	0	0
T2	5040	9	0	0
T3	10776	0	0	0
T47	1005	0	0	0
T48	3656	0	0	0
T49	10302	0	0	0
T50	15318	0	0	0
T51	1554	0	0	0
T52	10422	7	0	0
T53	7504	0	0	0
T54	1530	0	0	0
T63	0	12	0	0
T64	0	14	0	0
T93	0	19	0	0
T95	0	33	0	0
T112	0	86	0	0
T132	0	35	0	0
T133	0	5	0	0
T134	0	276	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3752	0	0
T2	5040	15	0	0
T3	10776	0	0	0
T47	1005	0	0	0
T48	3656	0	0	0
T49	10302	0	0	0
T50	15318	0	0	0
T51	1554	0	0	0
T52	10422	21	0	0
T53	7504	0	0	0
T54	1530	0	0	0
T61	0	6	0	0
T63	0	10	0	0
T64	0	17	0	0
T69	0	10	0	0
T93	0	25	0	0
T112	0	95	0	0
T133	0	16	0	0
T134	0	235	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3269	0	0
T2	5040	12	0	0
T3	10776	0	0	0
T47	1005	0	0	0
T48	3656	0	0	0
T49	10302	0	0	0
T50	15318	0	0	0
T51	1554	0	0	0
T52	10422	22	0	0
T53	7504	0	0	0
T54	1530	0	0	0
T61	0	6	0	0
T63	0	3	0	0
T64	0	16	0	0
T93	0	14	0	0
T95	0	20	0	0
T112	0	77	0	0
T133	0	8	0	0
T134	0	184	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3686	0	0
T2	5040	15	0	0
T3	10776	0	0	0
T47	1005	0	0	0
T48	3656	0	0	0
T49	10302	0	0	0
T50	15318	0	0	0
T51	1554	0	0	0
T52	10422	18	0	0
T53	7504	0	0	0
T54	1530	0	0	0
T61	0	6	0	0
T63	0	9	0	0
T64	0	11	0	0
T68	0	2	0	0
T93	0	11	0	0
T112	0	94	0	0
T133	0	20	0	0
T134	0	209	0	0