Unified Coverage Report :: Module :: kmac

Module : kmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.56	98.77	96.05	100.00	100.00	96.55	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	98.56	98.77	96.05	100.00	100.00	96.55	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.56	98.77	96.05	100.00	100.00	96.55	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	98.38	93.14	99.93	95.45	96.04	98.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
gen_entropy.u_entropy	99.29	100.00	95.74	100.00	100.00	100.00	100.00
gen_entropy.u_prim_sync_reqack_data	95.83	100.00	83.33			100.00	100.00
intr_fifo_empty	93.75	100.00	75.00			100.00	100.00
intr_kmac_done	93.75	100.00	75.00			100.00	100.00
intr_kmac_err	93.75	100.00	75.00			100.00	100.00
kmac_csr_assert	100.00						100.00
sha3pad_assert_cov_if	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_app_intf	97.42	97.45	90.82		100.00	98.82	100.00
u_errchk	96.60	95.06	94.59		100.00	93.33	100.00
u_kmac_core	95.80	98.88	92.86	100.00	100.00	91.38	91.67
u_msgfifo	97.32	100.00	95.16	94.52	100.00	94.23	100.00
u_prim_lc_sync	100.00	100.00				100.00	100.00
u_reg	98.99	99.41	96.63	100.00		98.94	100.00
u_sha3	96.50	98.83	95.67	100.00	88.10	96.40	100.00
u_sha3_done_sender	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00
u_staterd	89.71	89.72	80.83			88.30	100.00
u_tlul_adapter_msgfifo	79.67	86.78	73.83			76.83	81.25

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : kmac

	Line No.	Total	Covered	Percent
TOTAL		163	161	98.77
ALWAYS	342	0	0
ALWAYS	342	2	2	100.00
ALWAYS	348	1	0	0.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
ALWAYS	425	9	9	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
ALWAYS	484	6	6	100.00
ALWAYS	497	6	6	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	537	1	1	100.00
CONT_ASSIGN	541	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	544	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
ALWAYS	559	5	5	100.00
CONT_ASSIGN	569	1	1	100.00
CONT_ASSIGN	576	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	588	1	1	100.00
ALWAYS	608	3	3	100.00
CONT_ASSIGN	612	1	1	100.00
CONT_ASSIGN	631	1	1	100.00
CONT_ASSIGN	636	1	1	100.00
ALWAYS	639	7	7	100.00
CONT_ASSIGN	675	1	1	100.00
CONT_ASSIGN	680	1	1	100.00
CONT_ASSIGN	687	1	1	100.00
CONT_ASSIGN	697	1	1	100.00
ALWAYS	717	3	3	100.00
ALWAYS	721	28	28	100.00
ALWAYS	859	3	3	100.00
CONT_ASSIGN	867	1	1	100.00
CONT_ASSIGN	867	1	1	100.00
CONT_ASSIGN	938	1	1	100.00
CONT_ASSIGN	940	1	1	100.00
CONT_ASSIGN	970	1	1	100.00
CONT_ASSIGN	975	1	1	100.00
CONT_ASSIGN	976	1	1	100.00
CONT_ASSIGN	978	1	1	100.00
CONT_ASSIGN	981	0	0
ALWAYS	1099	0	0
ALWAYS	1099	2	2	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1325	1	1	100.00
CONT_ASSIGN	1339	1	1	100.00
CONT_ASSIGN	1346	1	1	100.00
CONT_ASSIGN	1351	1	1	100.00
ALWAYS	1357	6	5	83.33
CONT_ASSIGN	1366	1	1	100.00
CONT_ASSIGN	1368	1	1	100.00
ALWAYS	1380	4	4	100.00
CONT_ASSIGN	1386	1	1	100.00
ALWAYS	1409	4	4	100.00
ALWAYS	1419	3	3	100.00
CONT_ASSIGN	1430	1	1	100.00
CONT_ASSIGN	1434	1	1	100.00
CONT_ASSIGN	1436	1	1	100.00
CONT_ASSIGN	1436	1	1	100.00
CONT_ASSIGN	1436	1	1	100.00
CONT_ASSIGN	1436	1	1	100.00
CONT_ASSIGN	1436	1	1	100.00
CONT_ASSIGN	1436	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
342	1	1
343	1	1
348	0	1
417	1	1
418	1	1
422	1	1
425	1	1
426	1	1
427	1	1
428	1	1
430	1	1
432	1	1
436	1	1
440	1	1
444	1	1
460	1	1
461	1	1
462	1	1
465	1	1
469	1	1
470	1	1
474	1	1
477	1	1
484	1	1
485	1	1
486	1	1
487	1	1
488	1	1
489	1	1
			MISSING_ELSE
			MISSING_ELSE
497	1	1
498	1	1
499	1	1
500	1	1
501	1	1
502	1	1
			MISSING_ELSE
			MISSING_ELSE
514	1	1
521	1	1
524	1	1
525	1	1
526	1	1
529	5	5
530	5	5
533	1	1
535	1	1
537	1	1
541	1	1
543	1	1
544	1	1
547	1	1
548	1	1
551	1	1
559	1	1
560	1	1
561	1	1
562	1	1
564	1	1
569	1	1
576	1	1
577	1	1
578	1	1
588	1	1
608	2	2
609	1	1
612	1	1
631	1	1
636	1	1
639	1	1
641	1	1
646	1	1
650	1	1
654	1	1
658	1	1
662	1	1
675	1	1
680	1	1
687	1	1
697	1	1
717	3	3
721	1	1
723	1	1
724	1	1
726	1	1
728	1	1
730	1	1
731	1	1
734	1	1
737	1	1
743	1	1
744	1	1
746	1	1
751	1	1
752	1	1
753	1	1
755	1	1
761	1	1
766	1	1
767	1	1
769	1	1
771	1	1
777	1	1
778	1	1
780	1	1
786	1	1
787	1	1
799	1	1
800	1	1
			MISSING_ELSE
859	1	1
860	1	1
862	1	1
867	2	2
938	1	1
940	1	1
970	1	1
975	1	1
976	1	1
978	1	1
981		unreachable
1099	1	1
1100	1	1
1185	1	1
1325	1	1
1339	1	1
1346	1	1
1351	1	1
1357	1	1
1358	1	1
1359	1	1
1360	0	1
1361	1	1
1362	1	1
			MISSING_ELSE
1366	1	1
1368	1	1
1380	1	1
1381	1	1
1382	1	1
1383	1	1
			MISSING_ELSE
1386	1	1
1409	1	1
1410	1	1
1411	1	1
1413	1	1
			MISSING_ELSE
1419	1	1
1420	1	1
1423	1	1
1430	1	1
1434	1	1
1436	6	6

---

Cond Coverage for Module : kmac

	Total	Covered	Percent
Conditions	76	73	96.05
Logical	76	73	96.05
Non-Logical	0	0
Event	0	0

 LINE       422
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       460
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       461
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       462
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       474
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       526
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T15,T17,T33

 LINE       537
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T17,T33,T76

 LINE       541
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T28,T36
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       548
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T4,T5,T6

 LINE       561
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T9,T96
1	1	Covered	T4,T5,T6

 LINE       561
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       561
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T4,T5,T6
1	-	Covered	T4,T5,T6

 LINE       569
 EXPRESSION (reg2hw.cfg_shadowed.err_processed.q & reg2hw.cfg_shadowed.err_processed.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T22,T28,T36
1	1	Covered	T22,T28,T36

 LINE       612
 EXPRESSION (((~msgfifo_empty_q)) & msgfifo_empty)
             ----------1---------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       631
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T4,T5,T6
0	0	0	1	Covered	T4,T6,T71
0	0	1	0	Covered	T84,T85,T77
0	1	0	0	Covered	T4,T6,T10
1	0	0	0	Covered	T12,T13,T14

 LINE       675
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T4,T5,T6
0	0	0	1	Covered	T7,T8,T9
0	0	1	0	Covered	T7,T8,T9
0	1	0	0	Covered	T7,T8,T9
1	0	0	0	Covered	T7,T8,T9

 LINE       687
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T4,T5,T6
0	0	0	0	0	1	Covered	T7,T8,T9
0	0	0	0	1	0	Covered	T7,T8,T9
0	0	0	1	0	0	Covered	T7,T8,T9
0	0	1	0	0	0	Covered	T7,T8,T9
0	1	0	0	0	0	Covered	T7,T8,T9
1	0	0	0	0	0	Covered	T7,T8,T9

 LINE       728
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       730
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       744
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T6,T12,T13
1	Covered	T4,T5,T6

 LINE       970
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       1100
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       1339
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T29,T97,T98
1	0	Covered	T4,T5,T6
1	1	Covered	T29,T97,T98

 LINE       1339
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T29,T97,T98
1	0	Covered	T4,T5,T6
1	1	Covered	T29,T97,T98

 LINE       1368
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T4,T5,T6
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T7,T8,T9
0	0	1	0	0	Covered	T10,T11,T7
0	1	0	0	0	Covered	T7,T8,T9
1	0	0	0	0	Not Covered

---

Toggle Coverage for Module : kmac

	Total	Covered	Percent
Totals	71	71	100.00
Total Bits	6534	6534	100.00
Total Bits 0->1	3267	3267	100.00
Total Bits 1->0	3267	3267	100.00

Ports	71	71	100.00
Port Bits	6534	6534	100.00
Port Bits 0->1	3267	3267	100.00
Port Bits 1->0	3267	3267	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T48	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T2,T3,T48	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T2,T3,T48	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T49	Yes	T1,T3,T49	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T49,T53,T54	Yes	T49,T53,T54	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T3,T48	Yes	T2,T3,T48	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T3,T48	Yes	T2,T3,T48	OUTPUT
keymgr_key_i.key[0][0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][4]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][6:5]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][7]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][8]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][11:9]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][13:12]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][15:14]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][17]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][19:18]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][22:20]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][23]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][27:24]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][28]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][29]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][33:30]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][34]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][37:35]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][42:38]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][44:43]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][46:45]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][48:47]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][49]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][51:50]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][52]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][53]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][55:54]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][56]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][60:57]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][62:61]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][69:63]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][71:70]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][72]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][74:73]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][76:75]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][80:77]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][83:81]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][84]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][85]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][88:86]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][91:89]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][92]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][96:93]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][99:97]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][100]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][101]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][102]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][103]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][105:104]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][106]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][107]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][109:108]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][117:110]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][118]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][119]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][120]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][123:121]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][124]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][125]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][128:126]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][129]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][130]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][133:131]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][135:134]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][136]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][140:137]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][141]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][143:142]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][146:144]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][147]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][148]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][150:149]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][151]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][152]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][155:153]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][156]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][161:157]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][163:162]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][165:164]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][166]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][168:167]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][169]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][170]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][174:171]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][175]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][176]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][177]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][178]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][181:179]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][182]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][184:183]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][185]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][186]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][187]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][188]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][189]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][190]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][191]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][194:192]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][198:195]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][200:199]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][203:201]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][204]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][205]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][206]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][207]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][209:208]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][210]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][213:211]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][214]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][215]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][218:216]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][219]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][221:220]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][223:222]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][225:224]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][228:226]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][229]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][230]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][231]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][233:232]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][234]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][236:235]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][239:237]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][241:240]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][242]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][243]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][245:244]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][246]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][248:247]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][249]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][251:250]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][252]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][254:253]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[0][255]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][7:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][9:8]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][11:10]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][15:12]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][19:18]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][20]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][22:21]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][24:23]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][30:25]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][34:31]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][38:35]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][39]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][40]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][41]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][43:42]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][45:44]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][46]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][47]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][49:48]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][50]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][51]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][54:52]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][55]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][56]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][57]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][58]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][59]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][60]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][61]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][64:62]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][67:65]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][68]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][69]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][71:70]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][72]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][74:73]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][75]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][76]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][80:77]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][81]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][83:82]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][86:84]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][88:87]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][89]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][90]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][92:91]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][93]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][98:94]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][99]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][105:100]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][106]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][107]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][115:108]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][117:116]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][118]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][121:119]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][122]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][125:123]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][127:126]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][128]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][129]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][131:130]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][132]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][135:133]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][139:136]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][140]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][141]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][146:142]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][148:147]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][150:149]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][151]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][152]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][154:153]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][155]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][157:156]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][158]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][159]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][163:160]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][167:164]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][168]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][172:169]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][173]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][174]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][175]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][181:176]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][182]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][186:183]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][187]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][188]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][189]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][190]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][192:191]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][193]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][194]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][196:195]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][197]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][199:198]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][209:200]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][210]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][211]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][212]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][214:213]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][215]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][216]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][222:217]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][226:223]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][230:227]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][233:231]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][235:234]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][238:236]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][239]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][241:240]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][246:242]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][248:247]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][250:249]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][253:251]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][254]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.key[1][255]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
keymgr_key_i.valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
app_i[0].last	Yes	Yes	T6,T12,T13	Yes	T6,T12,T13	INPUT
app_i[0].strb[7:0]	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	INPUT
app_i[0].data[63:0]	Yes	Yes	T6,T12,T22	Yes	T6,T12,T22	INPUT
app_i[0].valid	Yes	Yes	T6,T10,T12	Yes	T6,T10,T12	INPUT
app_i[1].last	Yes	Yes	T12,T13,T15	Yes	T12,T13,T14	INPUT
app_i[1].strb[7:0]	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	INPUT
app_i[1].data[63:0]	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	INPUT
app_i[1].valid	Yes	Yes	T10,T12,T13	Yes	T10,T12,T13	INPUT
app_i[2].last	Yes	Yes	T6,T12,T13	Yes	T6,T12,T13	INPUT
app_i[2].strb[7:0]	Yes	Yes	T15,T17,T18	Yes	T15,T17,T18	INPUT
app_i[2].data[63:0]	Yes	Yes	T6,T12,T13	Yes	T6,T12,T13	INPUT
app_i[2].valid	Yes	Yes	T6,T10,T12	Yes	T6,T10,T12	INPUT
app_o[0].error	Yes	Yes	T2,T3,T48	Yes	T2,T3,T48	OUTPUT
app_o[0].digest_share1[383:0]	Yes	Yes	T6,T12,T13	Yes	T6,T12,T13	OUTPUT
app_o[0].digest_share0[383:0]	Yes	Yes	T6,T12,T13	Yes	T6,T12,T13	OUTPUT
app_o[0].done	Yes	Yes	T6,T12,T13	Yes	T6,T12,T13	OUTPUT
app_o[0].ready	Yes	Yes	T6,T12,T22	Yes	T6,T12,T22	OUTPUT
app_o[1].error	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	OUTPUT
app_o[1].digest_share1[383:0]	Yes	Yes	T12,T13,T15	Yes	T12,T13,T15	OUTPUT
app_o[1].digest_share0[383:0]	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	OUTPUT
app_o[1].done	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	OUTPUT
app_o[1].ready	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	OUTPUT
app_o[2].error	Yes	Yes	T12,T13,T15	Yes	T12,T13,T15	OUTPUT
app_o[2].digest_share1[383:0]	Yes	Yes	T6,T12,T13	Yes	T6,T12,T13	OUTPUT
app_o[2].digest_share0[383:0]	Yes	Yes	T12,T13,T15	Yes	T12,T13,T15	OUTPUT
app_o[2].done	Yes	Yes	T6,T12,T13	Yes	T6,T12,T13	OUTPUT
app_o[2].ready	Yes	Yes	T6,T12,T13	Yes	T6,T12,T13	OUTPUT
entropy_o.edn_req	Yes	Yes	T63,T5,T12	Yes	T63,T5,T12	OUTPUT
entropy_i.edn_bus[31:0]	Yes	Yes	T63,T5,T12	Yes	T63,T5,T12	INPUT
entropy_i.edn_fips	Yes	Yes	T63,T5,T12	Yes	T63,T5,T12	INPUT
entropy_i.edn_ack	Yes	Yes	T63,T5,T12	Yes	T63,T5,T12	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T10,T99,T100	Yes	T10,T99,T100	INPUT
intr_kmac_done_o	Yes	Yes	T47,T101,T102	Yes	T47,T101,T102	OUTPUT
intr_fifo_empty_o	Yes	Yes	T47,T51,T66	Yes	T47,T51,T66	OUTPUT
intr_kmac_err_o	Yes	Yes	T3,T49,T67	Yes	T3,T49,T67	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T2,T3,T48	Yes	T2,T3,T48	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : kmac

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	769	Covered	T1
KmacIdle	737	Covered	T1
KmacKeyBlock	744	Covered	T1
KmacMsgFeed	734	Covered	T1
KmacPrefix	731	Covered	T1
KmacTerminalError	786	Covered	T1

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	778	Covered	T1
KmacDigest->KmacTerminalError	800	Covered	T1
KmacIdle->KmacMsgFeed	734	Covered	T1
KmacIdle->KmacPrefix	731	Covered	T1
KmacIdle->KmacTerminalError	800	Covered	T1
KmacKeyBlock->KmacMsgFeed	753	Covered	T1
KmacKeyBlock->KmacTerminalError	800	Covered	T1
KmacMsgFeed->KmacDigest	769	Covered	T1
KmacMsgFeed->KmacIdle	766	Covered	T1
KmacMsgFeed->KmacTerminalError	800	Covered	T1
KmacPrefix->KmacKeyBlock	744	Covered	T1
KmacPrefix->KmacMsgFeed	744	Covered	T1
KmacPrefix->KmacTerminalError	800	Covered	T1

---

Branch Coverage for Module : kmac

	Line No.	Total	Covered	Percent
Branches		58	56	96.55
TERNARY	422	2	2	100.00
CASE	430	6	5	83.33
IF	484	3	3	100.00
IF	559	3	3	100.00
IF	608	2	2	100.00
CASE	641	6	6	100.00
IF	717	2	2	100.00
CASE	726	15	15	100.00
IF	799	2	2	100.00
TERNARY	1100	2	2	100.00
IF	1357	4	3	75.00
IF	1380	3	3	100.00
IF	1409	3	3	100.00
IF	1419	2	2	100.00
IF	497	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	422	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	430	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Covered	T4,T5,T6
CmdProcess	Covered	T4,T5,T6
CmdManualRun	Covered	T4,T5,T6
CmdDone	Covered	T4,T5,T6
CmdNone	Covered	T4,T5,T6
default	Not Covered

	LineNo.	Expression
-1-:	484	if ((!rst_ni))
-2-:	486	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	559	if ((!rst_ni))
-2-:	561	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	608	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	641	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Covered	T4,T6,T10
errchecker_err.valid	Covered	T4,T6,T71
sha3_err.valid	Covered	T12,T13,T14
entropy_err.valid	Covered	T84,T85,T77
msgfifo_err.valid	Covered	T7,T8,T9
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	717	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	726	case (kmac_st)
-2-:	728	if ((kmac_cmd == CmdStart))
-3-:	730	if ((CShake == app_sha3_mode))
-4-:	743	if (sha3_block_processed)
-5-:	744	(app_kmac_en) ? 
-6-:	752	if (sha3_block_processed)
-7-:	761	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	767	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	777	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T4,T5,T6
KmacIdle	1	0	-	-	-	-	-	-	Covered	T4,T5,T6
KmacIdle	0	-	-	-	-	-	-	-	Covered	T4,T5,T6
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T4,T5,T6
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T6,T12,T13
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T4,T5,T6
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T4,T5,T6
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T4,T5,T6
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T6,T12,T13
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T4,T5,T6
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T4,T5,T6
KmacDigest	-	-	-	-	-	-	-	1	Covered	T4,T5,T6
KmacDigest	-	-	-	-	-	-	-	0	Covered	T4,T5,T6
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T10,T11,T7
default	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	799	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T7
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	1100	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	1357	if ((!rst_ni))
-2-:	1359	if (alert_recov_operation)
-3-:	1361	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Not Covered
0	0	1	Covered	T22,T28,T36
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	1380	if ((!rst_ni))
-2-:	1382	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T10,T11,T7
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	1409	if ((!rst_ni))
-2-:	1411	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T10,T11,T7
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	1419	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	497	if ((!rst_ni))
-2-:	499	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

---

Assert Coverage for Module : kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	2147483647	2147483647	0	0
CmdSparse_M	2147483647	1299951	0	0
EnMaskingKnown_A	2147483647	2147483647	0	0
EntropyReadyLatched_A	2147483647	341095	0	0
EntrySizeRegSameToEntrySizePkg_A	1049	1049	0	0
ErrProcessedLatched_A	2147483647	676	0	0
FifoEmpty_A	2147483647	2147483647	0	0
FpvSecCmErrorCheckFsmCheck_A	2147483647	90	0	0
FpvSecCmKeccackFsmCheck_A	2147483647	90	0	0
FpvSecCmKeyIndexCountCheck_A	2147483647	90	0	0
FpvSecCmKmacAppFsmCheck_A	2147483647	90	0	0
FpvSecCmKmacCoreFsmCheck_A	2147483647	90	0	0
FpvSecCmKmacFsmCheck_A	2147483647	90	0	0
FpvSecCmRegWeOnehotCheck_A	2147483647	90	0	0
FpvSecCmRoundCountCheck_A	2147483647	90	0	0
FpvSecCmSHA3FsmCheck_A	2147483647	90	0	0
FpvSecCmSHA3padFsmCheck_A	2147483647	90	0	0
FpvSecCmSentMsgCountCheck_A	2147483647	90	0	0
KmacCmd_A	2147483647	2147483647	0	0
KmacDone_A	2147483647	2147483647	0	0
KmacErr_A	2147483647	2147483647	0	0
KmacStKnown_A	2147483647	2147483647	0	0
NumAlerts2_A	1049	1049	0	0
NumEntriesRegSameToNumEntriesPkg_A	1049	1049	0	0
PrefixRegSameToPrefixPkg_A	1049	1049	0	0
SecretKeyDivideBy32_A	1049	1049	0	0
Sha3AbsorbedPulse_A	2147483647	350256	0	0
TlOAReadyKnown_A	2147483647	2147483647	0	0
TlODValidKnown_A	2147483647	2147483647	0	0
g_testassertion.FpvSecCmEntropyFsmCheck_A	2147483647	90	0	0
g_testassertion.FpvSecCmHashCountCheck_A	2147483647	90	0	0
g_testassertion.FpvSecCmMsgFifoRptrCheck_A	2147483647	90	0	0
g_testassertion.FpvSecCmMsgFifoWptrCheck_A	2147483647	90	0	0
g_testassertion.FpvSecCmPackerCountCheck_A	2147483647	90	0	0
g_testassertion.FpvSecCmSeedIdxCountCheck_A	2147483647	90	0	0
u_state_regs_A	2147483647	2147483647	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	108871	108775	0	0
T5	101041	101031	0	0
T6	218586	218536	0	0
T10	22515	22364	0	0
T12	186166	186107	0	0
T22	64882	64803	0	0
T23	262412	262411	0	0
T24	478610	478603	0	0
T25	10769	10684	0	0
T30	129182	129100	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1299951	0	0
T4	108871	271	0	0
T5	101041	495	0	0
T6	218586	533	0	0
T10	22515	15	0	0
T12	186166	1790	0	0
T22	64882	2	0	0
T23	262412	7515	0	0
T24	478610	986	0	0
T25	10769	30	0	0
T30	129182	90	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	108871	108775	0	0
T5	101041	101031	0	0
T6	218586	218536	0	0
T10	22515	22364	0	0
T12	186166	186107	0	0
T22	64882	64803	0	0
T23	262412	262411	0	0
T24	478610	478603	0	0
T25	10769	10684	0	0
T30	129182	129100	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	341095	0	0
T4	108871	40	0	0
T5	101041	70	0	0
T6	218586	77	0	0
T10	22515	3	0	0
T12	186166	389	0	0
T22	64882	12	0	0
T23	262412	2262	0	0
T24	478610	302	0	0
T25	10769	9	0	0
T30	129182	12	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049	1049	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T30	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	676	0	0
T13	404858	0	0	0
T22	64882	12	0	0
T23	262412	0	0	0
T24	478610	0	0	0
T25	10769	0	0	0
T26	191881	0	0	0
T27	459257	0	0	0
T28	27164	4	0	0
T29	1030	0	0	0
T31	512262	0	0	0
T36	0	9	0	0
T37	0	12	0	0
T46	0	2	0	0
T84	0	14	0	0
T85	0	2	0	0
T103	0	14	0	0
T104	0	6	0	0
T105	0	3	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	108871	108775	0	0
T5	101041	101031	0	0
T6	218586	218536	0	0
T10	22515	22364	0	0
T12	186166	186107	0	0
T22	64882	64803	0	0
T23	262412	262411	0	0
T24	478610	478603	0	0
T25	10769	10684	0	0
T30	129182	129100	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T7	470089	20	0	0
T8	445906	10	0	0
T9	0	20	0	0
T19	623149	0	0	0
T74	417467	0	0	0
T76	527904	0	0	0
T96	0	20	0	0
T104	42043	0	0	0
T105	17183	0	0	0
T106	0	20	0	0
T107	14621	0	0	0
T108	636175	0	0	0
T109	707457	0	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T7	470089	20	0	0
T8	445906	10	0	0
T9	0	20	0	0
T19	623149	0	0	0
T74	417467	0	0	0
T76	527904	0	0	0
T96	0	20	0	0
T104	42043	0	0	0
T105	17183	0	0	0
T106	0	20	0	0
T107	14621	0	0	0
T108	636175	0	0	0
T109	707457	0	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T7	470089	20	0	0
T8	445906	10	0	0
T9	0	20	0	0
T19	623149	0	0	0
T74	417467	0	0	0
T76	527904	0	0	0
T96	0	20	0	0
T104	42043	0	0	0
T105	17183	0	0	0
T106	0	20	0	0
T107	14621	0	0	0
T108	636175	0	0	0
T109	707457	0	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T7	470089	20	0	0
T8	445906	10	0	0
T9	0	20	0	0
T19	623149	0	0	0
T74	417467	0	0	0
T76	527904	0	0	0
T96	0	20	0	0
T104	42043	0	0	0
T105	17183	0	0	0
T106	0	20	0	0
T107	14621	0	0	0
T108	636175	0	0	0
T109	707457	0	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T7	470089	20	0	0
T8	445906	10	0	0
T9	0	20	0	0
T19	623149	0	0	0
T74	417467	0	0	0
T76	527904	0	0	0
T96	0	20	0	0
T104	42043	0	0	0
T105	17183	0	0	0
T106	0	20	0	0
T107	14621	0	0	0
T108	636175	0	0	0
T109	707457	0	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T7	470089	20	0	0
T8	445906	10	0	0
T9	0	20	0	0
T19	623149	0	0	0
T74	417467	0	0	0
T76	527904	0	0	0
T96	0	20	0	0
T104	42043	0	0	0
T105	17183	0	0	0
T106	0	20	0	0
T107	14621	0	0	0
T108	636175	0	0	0
T109	707457	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T7	470089	20	0	0
T8	445906	10	0	0
T9	0	20	0	0
T19	623149	0	0	0
T74	417467	0	0	0
T76	527904	0	0	0
T96	0	20	0	0
T104	42043	0	0	0
T105	17183	0	0	0
T106	0	20	0	0
T107	14621	0	0	0
T108	636175	0	0	0
T109	707457	0	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T7	470089	20	0	0
T8	445906	10	0	0
T9	0	20	0	0
T19	623149	0	0	0
T74	417467	0	0	0
T76	527904	0	0	0
T96	0	20	0	0
T104	42043	0	0	0
T105	17183	0	0	0
T106	0	20	0	0
T107	14621	0	0	0
T108	636175	0	0	0
T109	707457	0	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T7	470089	20	0	0
T8	445906	10	0	0
T9	0	20	0	0
T19	623149	0	0	0
T74	417467	0	0	0
T76	527904	0	0	0
T96	0	20	0	0
T104	42043	0	0	0
T105	17183	0	0	0
T106	0	20	0	0
T107	14621	0	0	0
T108	636175	0	0	0
T109	707457	0	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T7	470089	20	0	0
T8	445906	10	0	0
T9	0	20	0	0
T19	623149	0	0	0
T74	417467	0	0	0
T76	527904	0	0	0
T96	0	20	0	0
T104	42043	0	0	0
T105	17183	0	0	0
T106	0	20	0	0
T107	14621	0	0	0
T108	636175	0	0	0
T109	707457	0	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T7	470089	20	0	0
T8	445906	10	0	0
T9	0	20	0	0
T19	623149	0	0	0
T74	417467	0	0	0
T76	527904	0	0	0
T96	0	20	0	0
T104	42043	0	0	0
T105	17183	0	0	0
T106	0	20	0	0
T107	14621	0	0	0
T108	636175	0	0	0
T109	707457	0	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	108871	108775	0	0
T5	101041	101031	0	0
T6	218586	218536	0	0
T10	22515	22364	0	0
T12	186166	186107	0	0
T22	64882	64803	0	0
T23	262412	262411	0	0
T24	478610	478603	0	0
T25	10769	10684	0	0
T30	129182	129100	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	108871	108775	0	0
T5	101041	101031	0	0
T6	218586	218536	0	0
T10	22515	22364	0	0
T12	186166	186107	0	0
T22	64882	64803	0	0
T23	262412	262411	0	0
T24	478610	478603	0	0
T25	10769	10684	0	0
T30	129182	129100	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	108871	108775	0	0
T5	101041	101031	0	0
T6	218586	218536	0	0
T10	22515	22364	0	0
T12	186166	186107	0	0
T22	64882	64803	0	0
T23	262412	262411	0	0
T24	478610	478603	0	0
T25	10769	10684	0	0
T30	129182	129100	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	108871	108775	0	0
T5	101041	101031	0	0
T6	218586	218536	0	0
T10	22515	22364	0	0
T12	186166	186107	0	0
T22	64882	64803	0	0
T23	262412	262411	0	0
T24	478610	478603	0	0
T25	10769	10684	0	0
T30	129182	129100	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049	1049	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T30	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049	1049	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T30	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049	1049	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T30	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049	1049	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T30	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	350256	0	0
T4	108871	34	0	0
T5	101041	70	0	0
T6	218586	75	0	0
T10	22515	2	0	0
T12	186166	390	0	0
T22	64882	0	0	0
T23	262412	2337	0	0
T24	478610	310	0	0
T25	10769	9	0	0
T26	0	374	0	0
T30	129182	12	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	108871	108775	0	0
T5	101041	101031	0	0
T6	218586	218536	0	0
T10	22515	22364	0	0
T12	186166	186107	0	0
T22	64882	64803	0	0
T23	262412	262411	0	0
T24	478610	478603	0	0
T25	10769	10684	0	0
T30	129182	129100	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	108871	108775	0	0
T5	101041	101031	0	0
T6	218586	218536	0	0
T10	22515	22364	0	0
T12	186166	186107	0	0
T22	64882	64803	0	0
T23	262412	262411	0	0
T24	478610	478603	0	0
T25	10769	10684	0	0
T30	129182	129100	0	0

g_testassertion.FpvSecCmEntropyFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T7	470089	20	0	0
T8	445906	10	0	0
T9	0	20	0	0
T19	623149	0	0	0
T74	417467	0	0	0
T76	527904	0	0	0
T96	0	20	0	0
T104	42043	0	0	0
T105	17183	0	0	0
T106	0	20	0	0
T107	14621	0	0	0
T108	636175	0	0	0
T109	707457	0	0	0

g_testassertion.FpvSecCmHashCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T7	470089	20	0	0
T8	445906	10	0	0
T9	0	20	0	0
T19	623149	0	0	0
T74	417467	0	0	0
T76	527904	0	0	0
T96	0	20	0	0
T104	42043	0	0	0
T105	17183	0	0	0
T106	0	20	0	0
T107	14621	0	0	0
T108	636175	0	0	0
T109	707457	0	0	0

g_testassertion.FpvSecCmMsgFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T7	470089	20	0	0
T8	445906	10	0	0
T9	0	20	0	0
T19	623149	0	0	0
T74	417467	0	0	0
T76	527904	0	0	0
T96	0	20	0	0
T104	42043	0	0	0
T105	17183	0	0	0
T106	0	20	0	0
T107	14621	0	0	0
T108	636175	0	0	0
T109	707457	0	0	0

g_testassertion.FpvSecCmMsgFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T7	470089	20	0	0
T8	445906	10	0	0
T9	0	20	0	0
T19	623149	0	0	0
T74	417467	0	0	0
T76	527904	0	0	0
T96	0	20	0	0
T104	42043	0	0	0
T105	17183	0	0	0
T106	0	20	0	0
T107	14621	0	0	0
T108	636175	0	0	0
T109	707457	0	0	0

g_testassertion.FpvSecCmPackerCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T7	470089	20	0	0
T8	445906	10	0	0
T9	0	20	0	0
T19	623149	0	0	0
T74	417467	0	0	0
T76	527904	0	0	0
T96	0	20	0	0
T104	42043	0	0	0
T105	17183	0	0	0
T106	0	20	0	0
T107	14621	0	0	0
T108	636175	0	0	0
T109	707457	0	0	0

g_testassertion.FpvSecCmSeedIdxCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T7	470089	20	0	0
T8	445906	10	0	0
T9	0	20	0	0
T19	623149	0	0	0
T74	417467	0	0	0
T76	527904	0	0	0
T96	0	20	0	0
T104	42043	0	0	0
T105	17183	0	0	0
T106	0	20	0	0
T107	14621	0	0	0
T108	636175	0	0	0
T109	707457	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	108871	108775	0	0
T5	101041	101031	0	0
T6	218586	218536	0	0
T10	22515	22364	0	0
T12	186166	186107	0	0
T22	64882	64803	0	0
T23	262412	262411	0	0
T24	478610	478603	0	0
T25	10769	10684	0	0
T30	129182	129100	0	0