Unified Coverage Report :: Module :: kmac_core

Module : kmac_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	98.68	92.86		100.00	91.07	88.89

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_kmac_core	94.30	98.68	92.86		100.00	91.07	88.89

---

Module Instance : tb.dut.u_kmac_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	98.68	92.86		100.00	91.07	88.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.80	98.88	92.86	100.00	100.00	91.38	91.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_key_slicer[0].u_key_slicer	100.00	100.00					100.00
gen_key_slicer[1].u_key_slicer	100.00	100.00					100.00
u_key_index_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : kmac_core

	Line No.	Total	Covered	Percent
TOTAL		76	75	98.68
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	3	3	100.00
ALWAYS	164	30	30	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
ALWAYS	266	6	5	83.33
CONT_ASSIGN	285	1	1	100.00
ALWAYS	305	6	6	100.00
ALWAYS	336	6	6	100.00
ALWAYS	336	6	6	100.00
CONT_ASSIGN	370	1	1	100.00
CONT_ASSIGN	373	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
ALWAYS	418	6	6	100.00
CONT_ASSIGN	429	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
151	1	1
159	3	3
164	1	1
166	1	1
167	1	1
169	1	1
171	1	1
172	1	1
174	1	1
176	1	1
178	1	1
179	1	1
181	1	1
188	1	1
189	1	1
191	1	1
192	1	1
194	1	1
195	1	1
197	1	1
199	1	1
205	1	1
206	1	1
208	1	1
210	1	1
215	1	1
216	1	1
218	1	1
224	1	1
225	1	1
238	1	1
239	1	1
			MISSING_ELSE
249	1	1
250	1	1
251	1	1
252	1	1
256	1	1
258	1	1
263	1	1
266	1	1
267	1	1
268	1	1
269	0	1
270	1	1
272	1	1
			MISSING_ELSE
285	1	1
305	1	1
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
336	1	1
339	1	1
343	1	1
347	1	1
351	1	1
356	1	1
336	1	1
339	1	1
343	1	1
347	1	1
351	1	1
356	1	1
370	1	1
373	1	1
392	1	1
418	1	1
419	1	1
420	1	1
421	1	1
422	1	1
423	1	1
429	1	1

---

Cond Coverage for Module : kmac_core

	Total	Covered	Percent
Conditions	28	26	92.86
Logical	28	26	92.86
Non-Logical	0	0
Event	0	0

 LINE       178
 EXPRESSION (kmac_en_i && start_i)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T10
1	0	Covered	T5,T11,T18
1	1	Covered	T11,T18,T19

 LINE       205
 EXPRESSION (process_i || process_latched)
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T11,T18,T19
0	1	Not Covered
1	0	Covered	T11,T18,T19

 LINE       249
 EXPRESSION (en_kmac_datapath ? kmac_valid : fifo_valid_i)
             --------1-------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T18,T19

 LINE       250
 EXPRESSION (en_kmac_datapath ? kmac_data : fifo_data_i)
             --------1-------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T18,T19

 LINE       251
 EXPRESSION (en_kmac_datapath ? kmac_strb : fifo_strb_i)
             --------1-------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T18,T19

 LINE       252
 EXPRESSION (en_kmac_datapath ? 1'b0 : msg_ready_i)
             --------1-------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T18,T19

 LINE       256
 EXPRESSION (en_key_write ? '1 : '0)
             ------1-----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T18,T19

 LINE       258
 EXPRESSION (en_key_write ? key_sliced : ('{(*adjust*)default:'0}))
             ------1-----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T18,T19

 LINE       263
 EXPRESSION (kmac_en_i ? kmac_process : process_i)
             ----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T11,T18

 LINE       268
 EXPRESSION (process_i && ((!process_o)))
             ----1----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T10,T11
1	1	Not Covered

 LINE       392
 EXPRESSION (kmac_valid & msg_ready_i)
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T10,T11
1	0	Covered	T11,T18,T19
1	1	Covered	T11,T18,T19

 LINE       429
 EXPRESSION (key_index == block_addr_limit)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T18,T19

---

FSM Coverage for Module : kmac_core

Summary for FSM :: st

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	8	8	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StKey	179	Covered	T1
StKmacFlush	206	Covered	T1
StKmacIdle	181	Covered	T1
StKmacMsg	192	Covered	T1
StTerminalError	239	Covered	T1

transitions	Line No.	Covered	Tests
StKey->StKmacMsg	192	Covered	T1
StKey->StTerminalError	239	Covered	T1
StKmacFlush->StKmacIdle	216	Covered	T1
StKmacFlush->StTerminalError	239	Covered	T1
StKmacIdle->StKey	179	Covered	T1
StKmacIdle->StTerminalError	239	Covered	T1
StKmacMsg->StKmacFlush	206	Covered	T1
StKmacMsg->StTerminalError	239	Covered	T1

---

Branch Coverage for Module : kmac_core

	Line No.	Total	Covered	Percent
Branches		56	51	91.07
TERNARY	249	2	2	100.00
TERNARY	250	2	2	100.00
TERNARY	251	2	2	100.00
TERNARY	252	2	2	100.00
TERNARY	256	2	2	100.00
TERNARY	258	2	2	100.00
TERNARY	263	2	2	100.00
IF	159	2	2	100.00
CASE	176	10	10	100.00
IF	238	2	2	100.00
IF	266	4	3	75.00
CASE	305	6	5	83.33
CASE	418	6	5	83.33
CASE	336	6	5	83.33
CASE	336	6	5	83.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	249	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T18,T19
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	250	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T18,T19
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	251	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T18,T19
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	252	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T18,T19
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	256	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T18,T19
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	258	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T18,T19
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	263	(kmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T11,T18
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	159	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	176	case (st)
-2-:	178	if ((kmac_en_i && start_i))
-3-:	191	if (sent_blocksize)
-4-:	205	if ((process_i || process_latched))
-5-:	215	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StKmacIdle	1	-	-	-	Covered	T11,T18,T19
StKmacIdle	0	-	-	-	Covered	T4,T5,T6
StKey	-	1	-	-	Covered	T11,T18,T19
StKey	-	0	-	-	Covered	T11,T18,T19
StKmacMsg	-	-	1	-	Covered	T11,T18,T19
StKmacMsg	-	-	0	-	Covered	T11,T18,T19
StKmacFlush	-	-	-	1	Covered	T11,T18,T19
StKmacFlush	-	-	-	0	Covered	T11,T18,T19
StTerminalError	-	-	-	-	Covered	T6,T17,T12
default	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	238	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T6,T17,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	266	if ((!rst_ni))
-2-:	268	if ((process_i && (!process_o)))
-3-:	270	if ((process_o || prim_mubi_pkg::mubi4_test_true_strict(done_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Not Covered
0	0	1	Covered	T4,T10,T11
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	305	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T4,T5,T6
Key192	Covered	T4,T5,T10
Key256	Covered	T4,T5,T6
Key384	Covered	T4,T5,T10
Key512	Covered	T4,T5,T10
default	Not Covered

	LineNo.	Expression
-1-:	418	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T4,T5,T6
L224	Covered	T4,T18,T19
L256	Covered	T4,T5,T6
L384	Covered	T5,T18,T19
L512	Covered	T18,T19,T71
default	Not Covered

	LineNo.	Expression
-1-:	336	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T4,T5,T6
Key192	Covered	T4,T5,T10
Key256	Covered	T4,T5,T6
Key384	Covered	T4,T5,T10
Key512	Covered	T4,T5,T10
default	Not Covered

	LineNo.	Expression
-1-:	336	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T4,T5,T6
Key192	Covered	T4,T5,T10
Key256	Covered	T4,T5,T6
Key384	Covered	T4,T5,T10
Key512	Covered	T4,T5,T10
default	Not Covered

---

Assert Coverage for Module : kmac_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	8	88.89
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	8	88.89

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckOnlyInMessageState_A	2147483647	7786253	0	0
KeyDataStable_M	2147483647	1070610	0	0
KeyLengthStable_M	2147483647	280008	0	0
KmacEnStable_M	2147483647	23877	0	0
MaxKeyLenMatchToKey512_A	1050	1050	0	0
ModeStable_M	2147483647	35821	0	0
ProcessLatchedCleared_A	2147483647	0	0	0
StrengthStable_M	2147483647	42939	0	0
u_state_regs_A	2147483647	2147483647	0	0

AckOnlyInMessageState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7786253	0	0
T11	23098	109	0	0
T17	0	1149	0	0
T18	238257	230	0	0
T19	267191	101362	0	0
T20	869621	98696	0	0
T21	658479	0	0	0
T22	207157	0	0	0
T23	203607	0	0	0
T24	957373	4571	0	0
T25	1498	0	0	0
T41	0	2551	0	0
T50	904558	0	0	0
T51	0	9214	0	0
T52	0	7154	0	0
T72	0	109	0	0

KeyDataStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1070610	0	0
T5	70655	374	0	0
T6	4133	2	0	0
T10	153417	0	0	0
T11	23098	8	0	0
T17	0	194	0	0
T18	238257	2560	0	0
T19	267191	7338	0	0
T20	869621	4480	0	0
T21	658479	0	0	0
T22	207157	0	0	0
T24	0	1620	0	0
T25	1498	0	0	0
T26	0	374	0	0
T72	0	8	0	0

KeyLengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	280008	0	0
T4	654233	301	0	0
T5	70655	26	0	0
T6	4133	1	0	0
T10	153417	1814	0	0
T11	23098	1	0	0
T18	238257	86	0	0
T19	267191	393	0	0
T20	869621	149	0	0
T21	658479	323	0	0
T22	0	309	0	0
T25	1498	0	0	0

KmacEnStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	23877	0	0
T5	70655	22	0	0
T6	4133	0	0	0
T10	153417	0	0	0
T11	23098	1	0	0
T17	0	14	0	0
T18	238257	35	0	0
T19	267191	141	0	0
T20	869621	71	0	0
T21	658479	0	0	0
T22	207157	0	0	0
T24	0	77	0	0
T25	1498	0	0	0
T26	0	22	0	0
T27	0	18	0	0
T72	0	1	0	0

MaxKeyLenMatchToKey512_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050	1050	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T25	1	1	0	0

ModeStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35821	0	0
T5	70655	29	0	0
T6	4133	1	0	0
T10	153417	1	0	0
T11	23098	1	0	0
T17	0	30	0	0
T18	238257	37	0	0
T19	267191	238	0	0
T20	869621	71	0	0
T21	658479	0	0	0
T22	207157	0	0	0
T24	0	171	0	0
T25	1498	0	0	0
T26	0	26	0	0

ProcessLatchedCleared_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

StrengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	42939	0	0
T4	654233	2	0	0
T5	70655	25	0	0
T6	4133	3	0	0
T10	153417	2	0	0
T11	23098	2	0	0
T18	238257	69	0	0
T19	267191	289	0	0
T20	869621	96	0	0
T21	658479	2	0	0
T25	1498	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	654233	654227	0	0
T5	70655	70587	0	0
T6	4133	3994	0	0
T10	153417	153416	0	0
T11	23098	23029	0	0
T18	238257	238160	0	0
T19	267191	267139	0	0
T20	869621	869611	0	0
T21	658479	658472	0	0
T25	1498	1426	0	0

Line Coverage for Instance : tb.dut.u_kmac_core

	Line No.	Total	Covered	Percent
TOTAL		76	75	98.68
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	3	3	100.00
ALWAYS	164	30	30	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
ALWAYS	266	6	5	83.33
CONT_ASSIGN	285	1	1	100.00
ALWAYS	305	6	6	100.00
ALWAYS	336	6	6	100.00
ALWAYS	336	6	6	100.00
CONT_ASSIGN	370	1	1	100.00
CONT_ASSIGN	373	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
ALWAYS	418	6	6	100.00
CONT_ASSIGN	429	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
151	1	1
159	3	3
164	1	1
166	1	1
167	1	1
169	1	1
171	1	1
172	1	1
174	1	1
176	1	1
178	1	1
179	1	1
181	1	1
188	1	1
189	1	1
191	1	1
192	1	1
194	1	1
195	1	1
197	1	1
199	1	1
205	1	1
206	1	1
208	1	1
210	1	1
215	1	1
216	1	1
218	1	1
224	1	1
225	1	1
238	1	1
239	1	1
			MISSING_ELSE
249	1	1
250	1	1
251	1	1
252	1	1
256	1	1
258	1	1
263	1	1
266	1	1
267	1	1
268	1	1
269	0	1
270	1	1
272	1	1
			MISSING_ELSE
285	1	1
305	1	1
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
336	1	1
339	1	1
343	1	1
347	1	1
351	1	1
356	1	1
336	1	1
339	1	1
343	1	1
347	1	1
351	1	1
356	1	1
370	1	1
373	1	1
392	1	1
418	1	1
419	1	1
420	1	1
421	1	1
422	1	1
423	1	1
429	1	1

---

Cond Coverage for Instance : tb.dut.u_kmac_core

	Total	Covered	Percent
Conditions	28	26	92.86
Logical	28	26	92.86
Non-Logical	0	0
Event	0	0

 LINE       178
 EXPRESSION (kmac_en_i && start_i)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T10
1	0	Covered	T5,T11,T18
1	1	Covered	T11,T18,T19

 LINE       205
 EXPRESSION (process_i || process_latched)
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T11,T18,T19
0	1	Not Covered
1	0	Covered	T11,T18,T19

 LINE       249
 EXPRESSION (en_kmac_datapath ? kmac_valid : fifo_valid_i)
             --------1-------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T18,T19

 LINE       250
 EXPRESSION (en_kmac_datapath ? kmac_data : fifo_data_i)
             --------1-------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T18,T19

 LINE       251
 EXPRESSION (en_kmac_datapath ? kmac_strb : fifo_strb_i)
             --------1-------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T18,T19

 LINE       252
 EXPRESSION (en_kmac_datapath ? 1'b0 : msg_ready_i)
             --------1-------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T18,T19

 LINE       256
 EXPRESSION (en_key_write ? '1 : '0)
             ------1-----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T18,T19

 LINE       258
 EXPRESSION (en_key_write ? key_sliced : ('{(*adjust*)default:'0}))
             ------1-----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T18,T19

 LINE       263
 EXPRESSION (kmac_en_i ? kmac_process : process_i)
             ----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T11,T18

 LINE       268
 EXPRESSION (process_i && ((!process_o)))
             ----1----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T10,T11
1	1	Not Covered

 LINE       392
 EXPRESSION (kmac_valid & msg_ready_i)
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T10,T11
1	0	Covered	T11,T18,T19
1	1	Covered	T11,T18,T19

 LINE       429
 EXPRESSION (key_index == block_addr_limit)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T18,T19

---

FSM Coverage for Instance : tb.dut.u_kmac_core

Summary for FSM :: st

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StKey	179	Covered	T1
StKmacFlush	206	Covered	T1
StKmacIdle	181	Covered	T1
StKmacMsg	192	Covered	T1
StTerminalError	239	Covered	T1

transitions	Line No.	Covered	Tests	Exclude Annotation
StKey->StKmacMsg	192	Covered	T1
StKey->StTerminalError	239	Covered	T1
StKmacFlush->StKmacIdle	216	Covered	T1
StKmacFlush->StTerminalError	239	Excluded	T1	[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StKmacIdle->StKey	179	Covered	T1
StKmacIdle->StTerminalError	239	Covered	T1
StKmacMsg->StKmacFlush	206	Covered	T1
StKmacMsg->StTerminalError	239	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_kmac_core

	Line No.	Total	Covered	Percent
Branches		56	51	91.07
TERNARY	249	2	2	100.00
TERNARY	250	2	2	100.00
TERNARY	251	2	2	100.00
TERNARY	252	2	2	100.00
TERNARY	256	2	2	100.00
TERNARY	258	2	2	100.00
TERNARY	263	2	2	100.00
IF	159	2	2	100.00
CASE	176	10	10	100.00
IF	238	2	2	100.00
IF	266	4	3	75.00
CASE	305	6	5	83.33
CASE	418	6	5	83.33
CASE	336	6	5	83.33
CASE	336	6	5	83.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	249	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T18,T19
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	250	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T18,T19
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	251	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T18,T19
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	252	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T18,T19
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	256	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T18,T19
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	258	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T18,T19
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	263	(kmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T11,T18
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	159	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	176	case (st)
-2-:	178	if ((kmac_en_i && start_i))
-3-:	191	if (sent_blocksize)
-4-:	205	if ((process_i || process_latched))
-5-:	215	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StKmacIdle	1	-	-	-	Covered	T11,T18,T19
StKmacIdle	0	-	-	-	Covered	T4,T5,T6
StKey	-	1	-	-	Covered	T11,T18,T19
StKey	-	0	-	-	Covered	T11,T18,T19
StKmacMsg	-	-	1	-	Covered	T11,T18,T19
StKmacMsg	-	-	0	-	Covered	T11,T18,T19
StKmacFlush	-	-	-	1	Covered	T11,T18,T19
StKmacFlush	-	-	-	0	Covered	T11,T18,T19
StTerminalError	-	-	-	-	Covered	T6,T17,T12
default	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	238	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T6,T17,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	266	if ((!rst_ni))
-2-:	268	if ((process_i && (!process_o)))
-3-:	270	if ((process_o || prim_mubi_pkg::mubi4_test_true_strict(done_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Not Covered
0	0	1	Covered	T4,T10,T11
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	305	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T4,T5,T6
Key192	Covered	T4,T5,T10
Key256	Covered	T4,T5,T6
Key384	Covered	T4,T5,T10
Key512	Covered	T4,T5,T10
default	Not Covered

	LineNo.	Expression
-1-:	418	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T4,T5,T6
L224	Covered	T4,T18,T19
L256	Covered	T4,T5,T6
L384	Covered	T5,T18,T19
L512	Covered	T18,T19,T71
default	Not Covered

	LineNo.	Expression
-1-:	336	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T4,T5,T6
Key192	Covered	T4,T5,T10
Key256	Covered	T4,T5,T6
Key384	Covered	T4,T5,T10
Key512	Covered	T4,T5,T10
default	Not Covered

	LineNo.	Expression
-1-:	336	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T4,T5,T6
Key192	Covered	T4,T5,T10
Key256	Covered	T4,T5,T6
Key384	Covered	T4,T5,T10
Key512	Covered	T4,T5,T10
default	Not Covered

---

Assert Coverage for Instance : tb.dut.u_kmac_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	8	88.89
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	8	88.89

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckOnlyInMessageState_A	2147483647	7786253	0	0
KeyDataStable_M	2147483647	1070610	0	0
KeyLengthStable_M	2147483647	280008	0	0
KmacEnStable_M	2147483647	23877	0	0
MaxKeyLenMatchToKey512_A	1050	1050	0	0
ModeStable_M	2147483647	35821	0	0
ProcessLatchedCleared_A	2147483647	0	0	0
StrengthStable_M	2147483647	42939	0	0
u_state_regs_A	2147483647	2147483647	0	0

AckOnlyInMessageState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7786253	0	0
T11	23098	109	0	0
T17	0	1149	0	0
T18	238257	230	0	0
T19	267191	101362	0	0
T20	869621	98696	0	0
T21	658479	0	0	0
T22	207157	0	0	0
T23	203607	0	0	0
T24	957373	4571	0	0
T25	1498	0	0	0
T41	0	2551	0	0
T50	904558	0	0	0
T51	0	9214	0	0
T52	0	7154	0	0
T72	0	109	0	0

KeyDataStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1070610	0	0
T5	70655	374	0	0
T6	4133	2	0	0
T10	153417	0	0	0
T11	23098	8	0	0
T17	0	194	0	0
T18	238257	2560	0	0
T19	267191	7338	0	0
T20	869621	4480	0	0
T21	658479	0	0	0
T22	207157	0	0	0
T24	0	1620	0	0
T25	1498	0	0	0
T26	0	374	0	0
T72	0	8	0	0

KeyLengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	280008	0	0
T4	654233	301	0	0
T5	70655	26	0	0
T6	4133	1	0	0
T10	153417	1814	0	0
T11	23098	1	0	0
T18	238257	86	0	0
T19	267191	393	0	0
T20	869621	149	0	0
T21	658479	323	0	0
T22	0	309	0	0
T25	1498	0	0	0

KmacEnStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	23877	0	0
T5	70655	22	0	0
T6	4133	0	0	0
T10	153417	0	0	0
T11	23098	1	0	0
T17	0	14	0	0
T18	238257	35	0	0
T19	267191	141	0	0
T20	869621	71	0	0
T21	658479	0	0	0
T22	207157	0	0	0
T24	0	77	0	0
T25	1498	0	0	0
T26	0	22	0	0
T27	0	18	0	0
T72	0	1	0	0

MaxKeyLenMatchToKey512_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050	1050	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T25	1	1	0	0

ModeStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35821	0	0
T5	70655	29	0	0
T6	4133	1	0	0
T10	153417	1	0	0
T11	23098	1	0	0
T17	0	30	0	0
T18	238257	37	0	0
T19	267191	238	0	0
T20	869621	71	0	0
T21	658479	0	0	0
T22	207157	0	0	0
T24	0	171	0	0
T25	1498	0	0	0
T26	0	26	0	0

ProcessLatchedCleared_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

StrengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	42939	0	0
T4	654233	2	0	0
T5	70655	25	0	0
T6	4133	3	0	0
T10	153417	2	0	0
T11	23098	2	0	0
T18	238257	69	0	0
T19	267191	289	0	0
T20	869621	96	0	0
T21	658479	2	0	0
T25	1498	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	654233	654227	0	0
T5	70655	70587	0	0
T6	4133	3994	0	0
T10	153417	153416	0	0
T11	23098	23029	0	0
T18	238257	238160	0	0
T19	267191	267139	0	0
T20	869621	869611	0	0
T21	658479	658472	0	0
T25	1498	1426	0	0