Unified Coverage Report :: Module :: prim_sparse_fsm_flop

Module : prim_sparse_fsm_flop

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_state_regs	100.00	100.00					100.00
tb.dut.u_kmac_core.u_state_regs	100.00	100.00					100.00
tb.dut.u_sha3.u_state_regs	100.00	100.00					100.00
tb.dut.u_sha3.u_pad.u_state_regs	100.00	100.00					100.00
tb.dut.u_sha3.u_keccak.u_state_regs	100.00	100.00					100.00
tb.dut.u_app_intf.u_state_regs	100.00	100.00					100.00
tb.dut.u_errchk.u_state_regs	100.00	100.00					100.00
tb.dut.gen_entropy.u_entropy.u_state_regs	100.00	100.00					100.00

---

Module Instance : tb.dut.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_kmac_core.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.30	98.68	92.86		100.00	91.07	88.89	u_kmac_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_sha3.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.09	97.30	81.25		100.00	91.89	100.00	u_sha3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_sha3.u_pad.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	99.41	88.37		100.00	95.70	100.00	u_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_sha3.u_keccak.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.32	92.94	100.00		73.33	90.32	100.00	u_keccak

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_app_intf.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.40	98.92	89.47		100.00	98.59	100.00	u_app_intf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_errchk.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	94.44	94.59		100.00	93.10	100.00	u_errchk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_entropy.u_entropy.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.15	100.00	95.74		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

Line Coverage for Module : prim_sparse_fsm_flop

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	1	1
43	1	1
47	1	1
48	1	1
49	1	1
51	1	1

---

Assert Coverage for Module : prim_sparse_fsm_flop

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	8400	8400	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8400	8400	0	0
T4	8	8	0	0
T5	8	8	0	0
T6	8	8	0	0
T10	8	8	0	0
T11	8	8	0	0
T18	8	8	0	0
T19	8	8	0	0
T20	8	8	0	0
T21	8	8	0	0
T25	8	8	0	0

Line Coverage for Instance : tb.dut.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	1	1
43	1	1
47	1	1
48	1	1
49	1	1
51	1	1

---

Assert Coverage for Instance : tb.dut.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	1050	1050	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050	1050	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_kmac_core.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	1	1
43	1	1
47	1	1
48	1	1
49	1	1
51	1	1

---

Assert Coverage for Instance : tb.dut.u_kmac_core.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	1050	1050	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050	1050	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_sha3.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	1	1
43	1	1
47	1	1
48	1	1
49	1	1
51	1	1

---

Assert Coverage for Instance : tb.dut.u_sha3.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	1050	1050	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050	1050	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_sha3.u_pad.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	1	1
43	1	1
47	1	1
48	1	1
49	1	1
51	1	1

---

Assert Coverage for Instance : tb.dut.u_sha3.u_pad.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	1050	1050	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050	1050	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	1	1
43	1	1
47	1	1
48	1	1
49	1	1
51	1	1

---

Assert Coverage for Instance : tb.dut.u_sha3.u_keccak.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	1050	1050	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050	1050	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_app_intf.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	1	1
43	1	1
47	1	1
48	1	1
49	1	1
51	1	1

---

Assert Coverage for Instance : tb.dut.u_app_intf.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	1050	1050	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050	1050	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_errchk.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	1	1
43	1	1
47	1	1
48	1	1
49	1	1
51	1	1

---

Assert Coverage for Instance : tb.dut.u_errchk.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	1050	1050	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050	1050	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.gen_entropy.u_entropy.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	1	1
43	1	1
47	1	1
48	1	1
49	1	1
51	1	1

---

Assert Coverage for Instance : tb.dut.gen_entropy.u_entropy.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	1050	1050	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050	1050	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T25	1	1	0	0