Unified Coverage Report :: Module :: kmac_errchk

Module : kmac_errchk

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	94.44	94.59		100.00	93.10	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_errchk	96.43	94.44	94.59		100.00	93.10	100.00

---

Module Instance : tb.dut.u_errchk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	94.44	94.59		100.00	93.10	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.60	95.06	94.59		100.00	93.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : kmac_errchk

	Line No.	Total	Covered	Percent
TOTAL		72	68	94.44
ALWAYS	185	15	13	86.67
CONT_ASSIGN	234	1	1	100.00
ALWAYS	242	4	4	100.00
ALWAYS	248	4	4	100.00
ALWAYS	264	4	4	100.00
ALWAYS	276	6	6	100.00
ALWAYS	284	4	3	75.00
ALWAYS	307	6	6	100.00
ALWAYS	320	6	5	83.33
CONT_ASSIGN	374	1	1	100.00
ALWAYS	389	3	3	100.00
CONT_ASSIGN	397	1	1	100.00
ALWAYS	400	17	17	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
185	1	1
186	1	1
188	1	1
191	1	1
192	1	1
			MISSING_ELSE
198	1	1
199	1	1
			MISSING_ELSE
204	1	1
205	0	1
			MISSING_ELSE
211	1	1
212	1	1
			MISSING_ELSE
217	1	1
218	0	1
			MISSING_ELSE
223	1	1
224	1	1
234	1	1
242	2	2
243	2	2
			MISSING_ELSE
248	1	1
250	1	1
252	1	1
256	1	1
			MISSING_ELSE
			MISSING_ELSE
264	1	1
266	1	1
267	1	1
268	1	1
			MISSING_ELSE
			MISSING_ELSE
276	2	2
277	2	2
278	1	1
279	1	1
			MISSING_ELSE
284	1	1
286	1	1
287	1	1
288	0	1
			MISSING_ELSE
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
310	1	1
311	1	1
312	1	1
320	1	1
322	1	1
324	1	1
335	1	1
347	1	1
357	0	1
374	1	1
389	3	3
397	1	1
400	1	1
402	1	1
404	1	1
407	1	1
			MISSING_ELSE
412	1	1
413	1	1
			MISSING_ELSE
418	1	1
419	1	1
			MISSING_ELSE
424	1	1
425	1	1
426	1	1
427	1	1
			MISSING_ELSE
432	1	1
433	1	1
			MISSING_ELSE
439	1	1
451	1	1
452	1	1
			MISSING_ELSE

---

Cond Coverage for Module : kmac_errchk

	Total	Covered	Percent
Conditions	74	70	94.59
Logical	74	70	94.59
Non-Logical	0	0
Event	0	0

 LINE       204
 EXPRESSION (sw_cmd_i != CmdNone)
            ----------1----------

-1-	Status	Tests
0	Covered	T4,T10,T11
1	Not Covered

 LINE       217
 EXPRESSION (sw_cmd_i != CmdNone)
            ----------1----------

-1-	Status	Tests
0	Covered	T10,T19,T20
1	Not Covered

 LINE       234
 EXPRESSION (err_swsequence || (err_modestrength && ((!cfg_en_unsupported_modestrength_i))) || err_entropy_ready)
             -------1------    ------------------------------2-----------------------------    --------3--------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Not Covered
0	1	0	Covered	T86,T38,T87
1	0	0	Covered	T86,T38,T87

 LINE       234
 SUB-EXPRESSION (err_modestrength && ((!cfg_en_unsupported_modestrength_i)))
                 --------1-------    -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T86,T38,T87
1	1	Covered	T86,T38,T87

 LINE       250
 EXPRESSION ((st == StIdle) && (st_d == StMsgFeed))
             -------1------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T10,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T10,T11

 LINE       250
 SUB-EXPRESSION (st == StIdle)
                -------1------

-1-	Status	Tests
0	Covered	T4,T6,T10
1	Covered	T4,T5,T6

 LINE       250
 SUB-EXPRESSION (st_d == StMsgFeed)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T10,T11

 LINE       252
 EXPRESSION 
 Number  Term
      1  (((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512})) || (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256}))) )

-1-	Status	Tests
0	Covered	T86,T38,T87
1	Covered	T4,T10,T11

 LINE       252
 SUB-EXPRESSION 
 Number  Term
      1  ((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512})) || 
      2  (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256})))

-1-	-2-	Status	Tests
0	0	Covered	T86,T38,T87
0	1	Covered	T10,T11,T18
1	0	Covered	T4,T18,T19

 LINE       252
 SUB-EXPRESSION ((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512}))
                 ----------1---------    ------------------------2-----------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T18
1	0	Covered	T38,T87,T88
1	1	Covered	T4,T18,T19

 LINE       252
 SUB-EXPRESSION (cfg_mode_i == Sha3)
                ----------1---------

-1-	Status	Tests
0	Covered	T10,T11,T18
1	Covered	T4,T18,T19

 LINE       252
 SUB-EXPRESSION (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256}))
                 ------------------------1------------------------    ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T24
1	0	Covered	T86,T38,T87
1	1	Covered	T10,T11,T18

 LINE       252
 SUB-EXPRESSION ((cfg_mode_i == Shake) || (cfg_mode_i == CShake))
                 ----------1----------    -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T18,T19
0	1	Covered	T11,T18,T19
1	0	Covered	T10,T18,T19

 LINE       252
 SUB-EXPRESSION (cfg_mode_i == Shake)
                ----------1----------

-1-	Status	Tests
0	Covered	T4,T11,T18
1	Covered	T10,T18,T19

 LINE       252
 SUB-EXPRESSION (cfg_mode_i == CShake)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T10,T18
1	Covered	T11,T18,T19

 LINE       266
 EXPRESSION ((st == StIdle) && (st_d == StMsgFeed) && kmac_en_i)
             -------1------    ---------2---------    ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T18,T19
1	0	1	Covered	T5,T11,T18
1	1	0	Covered	T4,T10,T18
1	1	1	Covered	T11,T18,T19

 LINE       266
 SUB-EXPRESSION (st == StIdle)
                -------1------

-1-	Status	Tests
0	Covered	T4,T6,T10
1	Covered	T4,T5,T6

 LINE       266
 SUB-EXPRESSION (st_d == StMsgFeed)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T10,T11

 LINE       267
 EXPRESSION (cfg_prefix_6B_i != kmac_pkg::EncodedStringKMAC)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T11,T18,T19
1	Covered	T86,T38,T87

 LINE       278
 EXPRESSION (entropy_ready_pulse_i && (st == StIdle))
             ----------1----------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       278
 SUB-EXPRESSION (st == StIdle)
                -------1------

-1-	Status	Tests
0	Covered	T4,T6,T10
1	Covered	T4,T5,T6

 LINE       286
 EXPRESSION ((st == StIdle) && (st_d == StMsgFeed) && kmac_en_i)
             -------1------    ---------2---------    ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T18,T19
1	0	1	Covered	T5,T11,T18
1	1	0	Covered	T4,T10,T18
1	1	1	Covered	T11,T18,T19

 LINE       286
 SUB-EXPRESSION (st == StIdle)
                -------1------

-1-	Status	Tests
0	Covered	T4,T6,T10
1	Covered	T4,T5,T6

 LINE       286
 SUB-EXPRESSION (st_d == StMsgFeed)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T10,T11

 LINE       397
 EXPRESSION (block_swcmd ? st : st_d)
             -----1-----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T86,T38,T87

 LINE       404
 EXPRESSION (((!app_active_i)) && (sw_cmd_i == CmdStart))
             --------1--------    -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T38,T39,T40
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T10,T11

 LINE       404
 SUB-EXPRESSION (sw_cmd_i == CmdStart)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T10,T11

 LINE       412
 EXPRESSION (sw_cmd_i == CmdProcess)
            ------------1-----------

-1-	Status	Tests
0	Covered	T4,T10,T11
1	Covered	T4,T10,T11

 LINE       424
 EXPRESSION (sw_cmd_i == CmdManualRun)
            -------------1------------

-1-	Status	Tests
0	Covered	T4,T10,T11
1	Covered	T10,T19,T20

 LINE       426
 EXPRESSION (sw_cmd_i == CmdDone)
            ----------1----------

-1-	Status	Tests
0	Covered	T4,T10,T11
1	Covered	T4,T10,T11

---

FSM Coverage for Module : kmac_errchk

Summary for FSM :: st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	11	11	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAbsorbed	419	Covered	T1
StIdle	427	Covered	T1
StMsgFeed	407	Covered	T1
StProcessing	413	Covered	T1
StSqueezing	425	Covered	T1
StTerminalError	452	Covered	T1

transitions	Line No.	Covered	Tests
StAbsorbed->StIdle	427	Covered	T1
StAbsorbed->StSqueezing	425	Covered	T1
StAbsorbed->StTerminalError	452	Covered	T1
StIdle->StMsgFeed	407	Covered	T1
StIdle->StTerminalError	452	Covered	T1
StMsgFeed->StProcessing	413	Covered	T1
StMsgFeed->StTerminalError	452	Covered	T1
StProcessing->StAbsorbed	419	Covered	T1
StProcessing->StTerminalError	452	Covered	T1
StSqueezing->StAbsorbed	433	Covered	T1
StSqueezing->StTerminalError	452	Covered	T1

---

Branch Coverage for Module : kmac_errchk

	Line No.	Total	Covered	Percent
Branches		58	54	93.10
TERNARY	397	2	2	100.00
CASE	188	12	10	83.33
IF	242	3	3	100.00
IF	250	3	3	100.00
IF	266	3	3	100.00
CASE	307	6	6	100.00
CASE	322	5	4	80.00
IF	389	2	2	100.00
CASE	402	13	13	100.00
IF	451	2	2	100.00
IF	276	4	4	100.00
IF	286	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	397	(block_swcmd) ? 

Branches:

-1-	Status	Tests
1	Covered	T86,T38,T87
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	188	case (st)
-2-:	191	if ((!(sw_cmd_i inside {CmdNone, CmdStart})))
-3-:	198	if ((!(sw_cmd_i inside {CmdNone, CmdProcess})))
-4-:	204	if ((sw_cmd_i != CmdNone))
-5-:	211	if ((!(sw_cmd_i inside {CmdNone, CmdManualRun, CmdDone})))
-6-:	217	if ((sw_cmd_i != CmdNone))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
StIdle	1	-	-	-	-	Covered	T86,T38,T87
StIdle	0	-	-	-	-	Covered	T4,T5,T6
StMsgFeed	-	1	-	-	-	Covered	T86,T38,T88
StMsgFeed	-	0	-	-	-	Covered	T4,T10,T11
StProcessing	-	-	1	-	-	Not Covered
StProcessing	-	-	0	-	-	Covered	T4,T10,T11
StAbsorbed	-	-	-	1	-	Covered	T86,T38,T87
StAbsorbed	-	-	-	0	-	Covered	T4,T10,T11
StSqueezing	-	-	-	-	1	Not Covered
StSqueezing	-	-	-	-	0	Covered	T10,T19,T20
StTerminalError	-	-	-	-	-	Covered	T6,T17,T12
default	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	242	if ((!rst_ni))
-2-:	243	if ((!block_swcmd))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T86,T38,T87

	LineNo.	Expression
-1-:	250	if (((st == StIdle) && (st_d == StMsgFeed)))
-2-:	252	if ((!(((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512})) || (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256})))))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T86,T38,T87
1	0	Covered	T4,T10,T11
0	-	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	266	if ((((st == StIdle) && (st_d == StMsgFeed)) && kmac_en_i))
-2-:	267	if ((cfg_prefix_6B_i != kmac_pkg::EncodedStringKMAC))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T86,T38,T87
1	0	Covered	T11,T18,T19
0	-	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	307	case (st)

Branches:

-1-	Status	Tests
StIdle	Covered	T4,T5,T6
StMsgFeed	Covered	T4,T10,T11
StProcessing	Covered	T4,T10,T11
StAbsorbed	Covered	T4,T10,T11
StSqueezing	Covered	T10,T19,T20
default	Covered	T6,T17,T12

	LineNo.	Expression
-1-:	322	case (1'b1)

Branches:

-1-	Status	Tests
err_swsequence	Covered	T86,T38,T87
err_modestrength	Covered	T86,T38,T87
err_prefix	Covered	T86,T38,T87
err_entropy_ready	Not Covered
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	389	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	402	case (st)
-2-:	404	if (((!app_active_i) && (sw_cmd_i == CmdStart)))
-3-:	412	if ((sw_cmd_i == CmdProcess))
-4-:	418	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed_i))
-5-:	424	if ((sw_cmd_i == CmdManualRun))
-6-:	426	if ((sw_cmd_i == CmdDone))
-7-:	432	if (keccak_done_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
StIdle	1	-	-	-	-	-	Covered	T4,T10,T11
StIdle	0	-	-	-	-	-	Covered	T4,T5,T6
StMsgFeed	-	1	-	-	-	-	Covered	T4,T10,T11
StMsgFeed	-	0	-	-	-	-	Covered	T4,T10,T11
StProcessing	-	-	1	-	-	-	Covered	T4,T10,T11
StProcessing	-	-	0	-	-	-	Covered	T4,T10,T11
StAbsorbed	-	-	-	1	-	-	Covered	T10,T19,T20
StAbsorbed	-	-	-	0	1	-	Covered	T4,T10,T11
StAbsorbed	-	-	-	0	0	-	Covered	T4,T10,T11
StSqueezing	-	-	-	-	-	1	Covered	T10,T19,T20
StSqueezing	-	-	-	-	-	0	Covered	T10,T19,T20
StTerminalError	-	-	-	-	-	-	Covered	T6,T17,T12
default	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	451	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T6,T17,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	276	if ((!rst_ni))
-2-:	277	if (err_processed_i)
-3-:	278	if ((entropy_ready_pulse_i && (st == StIdle)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T5,T26,T27
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	286	if ((((st == StIdle) && (st_d == StMsgFeed)) && kmac_en_i))
-2-:	287	if ((!cfg_entropy_ready))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Covered	T11,T18,T19
0	-	Covered	T4,T5,T6

---

Assert Coverage for Module : kmac_errchk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ExpectedModeStrengthBits_A	1050	1050	0	0
ExpectedStSwCmdBits_A	1050	1050	0	0
StKnown_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

ExpectedModeStrengthBits_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050	1050	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T25	1	1	0	0

ExpectedStSwCmdBits_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050	1050	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T25	1	1	0	0

StKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	654233	654227	0	0
T5	70655	70587	0	0
T6	4133	3994	0	0
T10	153417	153416	0	0
T11	23098	23029	0	0
T18	238257	238160	0	0
T19	267191	267139	0	0
T20	869621	869611	0	0
T21	658479	658472	0	0
T25	1498	1426	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	654233	654227	0	0
T5	70655	70587	0	0
T6	4133	3994	0	0
T10	153417	153416	0	0
T11	23098	23029	0	0
T18	238257	238160	0	0
T19	267191	267139	0	0
T20	869621	869611	0	0
T21	658479	658472	0	0
T25	1498	1426	0	0

Line Coverage for Instance : tb.dut.u_errchk

	Line No.	Total	Covered	Percent
TOTAL		72	68	94.44
ALWAYS	185	15	13	86.67
CONT_ASSIGN	234	1	1	100.00
ALWAYS	242	4	4	100.00
ALWAYS	248	4	4	100.00
ALWAYS	264	4	4	100.00
ALWAYS	276	6	6	100.00
ALWAYS	284	4	3	75.00
ALWAYS	307	6	6	100.00
ALWAYS	320	6	5	83.33
CONT_ASSIGN	374	1	1	100.00
ALWAYS	389	3	3	100.00
CONT_ASSIGN	397	1	1	100.00
ALWAYS	400	17	17	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
185	1	1
186	1	1
188	1	1
191	1	1
192	1	1
			MISSING_ELSE
198	1	1
199	1	1
			MISSING_ELSE
204	1	1
205	0	1
			MISSING_ELSE
211	1	1
212	1	1
			MISSING_ELSE
217	1	1
218	0	1
			MISSING_ELSE
223	1	1
224	1	1
234	1	1
242	2	2
243	2	2
			MISSING_ELSE
248	1	1
250	1	1
252	1	1
256	1	1
			MISSING_ELSE
			MISSING_ELSE
264	1	1
266	1	1
267	1	1
268	1	1
			MISSING_ELSE
			MISSING_ELSE
276	2	2
277	2	2
278	1	1
279	1	1
			MISSING_ELSE
284	1	1
286	1	1
287	1	1
288	0	1
			MISSING_ELSE
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
310	1	1
311	1	1
312	1	1
320	1	1
322	1	1
324	1	1
335	1	1
347	1	1
357	0	1
374	1	1
389	3	3
397	1	1
400	1	1
402	1	1
404	1	1
407	1	1
			MISSING_ELSE
412	1	1
413	1	1
			MISSING_ELSE
418	1	1
419	1	1
			MISSING_ELSE
424	1	1
425	1	1
426	1	1
427	1	1
			MISSING_ELSE
432	1	1
433	1	1
			MISSING_ELSE
439	1	1
451	1	1
452	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_errchk

	Total	Covered	Percent
Conditions	74	70	94.59
Logical	74	70	94.59
Non-Logical	0	0
Event	0	0

 LINE       204
 EXPRESSION (sw_cmd_i != CmdNone)
            ----------1----------

-1-	Status	Tests
0	Covered	T4,T10,T11
1	Not Covered

 LINE       217
 EXPRESSION (sw_cmd_i != CmdNone)
            ----------1----------

-1-	Status	Tests
0	Covered	T10,T19,T20
1	Not Covered

 LINE       234
 EXPRESSION (err_swsequence || (err_modestrength && ((!cfg_en_unsupported_modestrength_i))) || err_entropy_ready)
             -------1------    ------------------------------2-----------------------------    --------3--------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Not Covered
0	1	0	Covered	T86,T38,T87
1	0	0	Covered	T86,T38,T87

 LINE       234
 SUB-EXPRESSION (err_modestrength && ((!cfg_en_unsupported_modestrength_i)))
                 --------1-------    -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T86,T38,T87
1	1	Covered	T86,T38,T87

 LINE       250
 EXPRESSION ((st == StIdle) && (st_d == StMsgFeed))
             -------1------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T10,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T10,T11

 LINE       250
 SUB-EXPRESSION (st == StIdle)
                -------1------

-1-	Status	Tests
0	Covered	T4,T6,T10
1	Covered	T4,T5,T6

 LINE       250
 SUB-EXPRESSION (st_d == StMsgFeed)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T10,T11

 LINE       252
 EXPRESSION 
 Number  Term
      1  (((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512})) || (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256}))) )

-1-	Status	Tests
0	Covered	T86,T38,T87
1	Covered	T4,T10,T11

 LINE       252
 SUB-EXPRESSION 
 Number  Term
      1  ((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512})) || 
      2  (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256})))

-1-	-2-	Status	Tests
0	0	Covered	T86,T38,T87
0	1	Covered	T10,T11,T18
1	0	Covered	T4,T18,T19

 LINE       252
 SUB-EXPRESSION ((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512}))
                 ----------1---------    ------------------------2-----------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T18
1	0	Covered	T38,T87,T88
1	1	Covered	T4,T18,T19

 LINE       252
 SUB-EXPRESSION (cfg_mode_i == Sha3)
                ----------1---------

-1-	Status	Tests
0	Covered	T10,T11,T18
1	Covered	T4,T18,T19

 LINE       252
 SUB-EXPRESSION (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256}))
                 ------------------------1------------------------    ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T24
1	0	Covered	T86,T38,T87
1	1	Covered	T10,T11,T18

 LINE       252
 SUB-EXPRESSION ((cfg_mode_i == Shake) || (cfg_mode_i == CShake))
                 ----------1----------    -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T18,T19
0	1	Covered	T11,T18,T19
1	0	Covered	T10,T18,T19

 LINE       252
 SUB-EXPRESSION (cfg_mode_i == Shake)
                ----------1----------

-1-	Status	Tests
0	Covered	T4,T11,T18
1	Covered	T10,T18,T19

 LINE       252
 SUB-EXPRESSION (cfg_mode_i == CShake)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T10,T18
1	Covered	T11,T18,T19

 LINE       266
 EXPRESSION ((st == StIdle) && (st_d == StMsgFeed) && kmac_en_i)
             -------1------    ---------2---------    ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T18,T19
1	0	1	Covered	T5,T11,T18
1	1	0	Covered	T4,T10,T18
1	1	1	Covered	T11,T18,T19

 LINE       266
 SUB-EXPRESSION (st == StIdle)
                -------1------

-1-	Status	Tests
0	Covered	T4,T6,T10
1	Covered	T4,T5,T6

 LINE       266
 SUB-EXPRESSION (st_d == StMsgFeed)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T10,T11

 LINE       267
 EXPRESSION (cfg_prefix_6B_i != kmac_pkg::EncodedStringKMAC)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T11,T18,T19
1	Covered	T86,T38,T87

 LINE       278
 EXPRESSION (entropy_ready_pulse_i && (st == StIdle))
             ----------1----------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       278
 SUB-EXPRESSION (st == StIdle)
                -------1------

-1-	Status	Tests
0	Covered	T4,T6,T10
1	Covered	T4,T5,T6

 LINE       286
 EXPRESSION ((st == StIdle) && (st_d == StMsgFeed) && kmac_en_i)
             -------1------    ---------2---------    ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T18,T19
1	0	1	Covered	T5,T11,T18
1	1	0	Covered	T4,T10,T18
1	1	1	Covered	T11,T18,T19

 LINE       286
 SUB-EXPRESSION (st == StIdle)
                -------1------

-1-	Status	Tests
0	Covered	T4,T6,T10
1	Covered	T4,T5,T6

 LINE       286
 SUB-EXPRESSION (st_d == StMsgFeed)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T10,T11

 LINE       397
 EXPRESSION (block_swcmd ? st : st_d)
             -----1-----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T86,T38,T87

 LINE       404
 EXPRESSION (((!app_active_i)) && (sw_cmd_i == CmdStart))
             --------1--------    -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T38,T39,T40
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T10,T11

 LINE       404
 SUB-EXPRESSION (sw_cmd_i == CmdStart)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T10,T11

 LINE       412
 EXPRESSION (sw_cmd_i == CmdProcess)
            ------------1-----------

-1-	Status	Tests
0	Covered	T4,T10,T11
1	Covered	T4,T10,T11

 LINE       424
 EXPRESSION (sw_cmd_i == CmdManualRun)
            -------------1------------

-1-	Status	Tests
0	Covered	T4,T10,T11
1	Covered	T10,T19,T20

 LINE       426
 EXPRESSION (sw_cmd_i == CmdDone)
            ----------1----------

-1-	Status	Tests
0	Covered	T4,T10,T11
1	Covered	T4,T10,T11

---

FSM Coverage for Instance : tb.dut.u_errchk

Summary for FSM :: st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	10	10	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAbsorbed	419	Covered	T1
StIdle	427	Covered	T1
StMsgFeed	407	Covered	T1
StProcessing	413	Covered	T1
StSqueezing	425	Covered	T1
StTerminalError	452	Covered	T1

transitions	Line No.	Covered	Tests	Exclude Annotation
StAbsorbed->StIdle	427	Covered	T1
StAbsorbed->StSqueezing	425	Covered	T1
StAbsorbed->StTerminalError	452	Covered	T1
StIdle->StMsgFeed	407	Covered	T1
StIdle->StTerminalError	452	Covered	T1
StMsgFeed->StProcessing	413	Covered	T1
StMsgFeed->StTerminalError	452	Covered	T1
StProcessing->StAbsorbed	419	Covered	T1
StProcessing->StTerminalError	452	Covered	T1
StSqueezing->StAbsorbed	433	Covered	T1
StSqueezing->StTerminalError	452	Excluded	T1	[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.

---

Branch Coverage for Instance : tb.dut.u_errchk

	Line No.	Total	Covered	Percent
Branches		58	54	93.10
TERNARY	397	2	2	100.00
CASE	188	12	10	83.33
IF	242	3	3	100.00
IF	250	3	3	100.00
IF	266	3	3	100.00
CASE	307	6	6	100.00
CASE	322	5	4	80.00
IF	389	2	2	100.00
CASE	402	13	13	100.00
IF	451	2	2	100.00
IF	276	4	4	100.00
IF	286	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	397	(block_swcmd) ? 

Branches:

-1-	Status	Tests
1	Covered	T86,T38,T87
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	188	case (st)
-2-:	191	if ((!(sw_cmd_i inside {CmdNone, CmdStart})))
-3-:	198	if ((!(sw_cmd_i inside {CmdNone, CmdProcess})))
-4-:	204	if ((sw_cmd_i != CmdNone))
-5-:	211	if ((!(sw_cmd_i inside {CmdNone, CmdManualRun, CmdDone})))
-6-:	217	if ((sw_cmd_i != CmdNone))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
StIdle	1	-	-	-	-	Covered	T86,T38,T87
StIdle	0	-	-	-	-	Covered	T4,T5,T6
StMsgFeed	-	1	-	-	-	Covered	T86,T38,T88
StMsgFeed	-	0	-	-	-	Covered	T4,T10,T11
StProcessing	-	-	1	-	-	Not Covered
StProcessing	-	-	0	-	-	Covered	T4,T10,T11
StAbsorbed	-	-	-	1	-	Covered	T86,T38,T87
StAbsorbed	-	-	-	0	-	Covered	T4,T10,T11
StSqueezing	-	-	-	-	1	Not Covered
StSqueezing	-	-	-	-	0	Covered	T10,T19,T20
StTerminalError	-	-	-	-	-	Covered	T6,T17,T12
default	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	242	if ((!rst_ni))
-2-:	243	if ((!block_swcmd))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T86,T38,T87

	LineNo.	Expression
-1-:	250	if (((st == StIdle) && (st_d == StMsgFeed)))
-2-:	252	if ((!(((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512})) || (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256})))))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T86,T38,T87
1	0	Covered	T4,T10,T11
0	-	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	266	if ((((st == StIdle) && (st_d == StMsgFeed)) && kmac_en_i))
-2-:	267	if ((cfg_prefix_6B_i != kmac_pkg::EncodedStringKMAC))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T86,T38,T87
1	0	Covered	T11,T18,T19
0	-	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	307	case (st)

Branches:

-1-	Status	Tests
StIdle	Covered	T4,T5,T6
StMsgFeed	Covered	T4,T10,T11
StProcessing	Covered	T4,T10,T11
StAbsorbed	Covered	T4,T10,T11
StSqueezing	Covered	T10,T19,T20
default	Covered	T6,T17,T12

	LineNo.	Expression
-1-:	322	case (1'b1)

Branches:

-1-	Status	Tests
err_swsequence	Covered	T86,T38,T87
err_modestrength	Covered	T86,T38,T87
err_prefix	Covered	T86,T38,T87
err_entropy_ready	Not Covered
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	389	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	402	case (st)
-2-:	404	if (((!app_active_i) && (sw_cmd_i == CmdStart)))
-3-:	412	if ((sw_cmd_i == CmdProcess))
-4-:	418	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed_i))
-5-:	424	if ((sw_cmd_i == CmdManualRun))
-6-:	426	if ((sw_cmd_i == CmdDone))
-7-:	432	if (keccak_done_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
StIdle	1	-	-	-	-	-	Covered	T4,T10,T11
StIdle	0	-	-	-	-	-	Covered	T4,T5,T6
StMsgFeed	-	1	-	-	-	-	Covered	T4,T10,T11
StMsgFeed	-	0	-	-	-	-	Covered	T4,T10,T11
StProcessing	-	-	1	-	-	-	Covered	T4,T10,T11
StProcessing	-	-	0	-	-	-	Covered	T4,T10,T11
StAbsorbed	-	-	-	1	-	-	Covered	T10,T19,T20
StAbsorbed	-	-	-	0	1	-	Covered	T4,T10,T11
StAbsorbed	-	-	-	0	0	-	Covered	T4,T10,T11
StSqueezing	-	-	-	-	-	1	Covered	T10,T19,T20
StSqueezing	-	-	-	-	-	0	Covered	T10,T19,T20
StTerminalError	-	-	-	-	-	-	Covered	T6,T17,T12
default	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	451	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T6,T17,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	276	if ((!rst_ni))
-2-:	277	if (err_processed_i)
-3-:	278	if ((entropy_ready_pulse_i && (st == StIdle)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T5,T26,T27
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	286	if ((((st == StIdle) && (st_d == StMsgFeed)) && kmac_en_i))
-2-:	287	if ((!cfg_entropy_ready))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Covered	T11,T18,T19
0	-	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_errchk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ExpectedModeStrengthBits_A	1050	1050	0	0
ExpectedStSwCmdBits_A	1050	1050	0	0
StKnown_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

ExpectedModeStrengthBits_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050	1050	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T25	1	1	0	0

ExpectedStSwCmdBits_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050	1050	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T25	1	1	0	0

StKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	654233	654227	0	0
T5	70655	70587	0	0
T6	4133	3994	0	0
T10	153417	153416	0	0
T11	23098	23029	0	0
T18	238257	238160	0	0
T19	267191	267139	0	0
T20	869621	869611	0	0
T21	658479	658472	0	0
T25	1498	1426	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	654233	654227	0	0
T5	70655	70587	0	0
T6	4133	3994	0	0
T10	153417	153416	0	0
T11	23098	23029	0	0
T18	238257	238160	0	0
T19	267191	267139	0	0
T20	869621	869611	0	0
T21	658479	658472	0	0
T25	1498	1426	0	0