Design subhierarchy
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NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
 gen_entropy.u_entropy 99.29 100.00 95.74 100.00 100.00 100.00 100.00
 gen_entropy.u_prim_sync_reqack_data 95.83 100.00 83.33 100.00 100.00
intr_fifo_empty 93.75 100.00 75.00 100.00 100.00
intr_kmac_done 93.75 100.00 75.00 100.00 100.00
intr_kmac_err 93.75 100.00 75.00 100.00 100.00
kmac_csr_assert 100.00 100.00
sha3pad_assert_cov_if 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
 u_app_intf 96.98 97.45 89.80 100.00 97.65 100.00
 u_errchk 96.60 95.06 94.59 100.00 93.33 100.00
 u_kmac_core 95.80 98.88 92.86 100.00 100.00 91.38 91.67
 u_msgfifo 97.32 100.00 95.16 94.52 100.00 94.23 100.00
 u_prim_lc_sync 100.00 100.00 100.00 100.00
 u_reg 98.99 99.41 96.63 100.00 98.94 100.00
 u_sha3 96.90 98.83 95.67 100.00 90.48 96.40 100.00
 u_sha3_done_sender 100.00 100.00 100.00 100.00
 u_state_regs 100.00 100.00 100.00 100.00
 u_staterd 89.71 89.72 80.83 88.30 100.00
 u_tlul_adapter_msgfifo 79.67 86.78 73.83 76.83 81.25