Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sha3
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.45 97.30 81.25 81.82 91.89 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sha3 94.09 97.30 81.25 100.00 91.89 100.00



Module Instance : tb.dut.u_sha3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.09 97.30 81.25 100.00 91.89 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.90 98.83 95.67 100.00 90.48 96.40 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.56 98.77 96.05 100.00 100.00 96.55 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_keccak 94.72 98.81 98.84 100.00 73.33 97.36 100.00
u_pad 97.27 99.45 88.37 100.00 100.00 95.79 100.00
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : sha3
Line No.TotalCoveredPercent
TOTAL747297.30
CONT_ASSIGN13111100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN15911100.00
ALWAYS16633100.00
CONT_ASSIGN17111100.00
ALWAYS17566100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18511100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18811100.00
ALWAYS19533100.00
ALWAYS2053838100.00
ALWAYS30033100.00
ALWAYS317121083.33
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
131 1 1
137 1 1
141 1 1
159 1 1
166 2 2
167 1 1
171 1 1
175 2 2
176 2 2
177 1 1
178 1 1
MISSING_ELSE
182 1 1
185 1 1
186 1 1
188 1 1
195 3 3
205 1 1
208 1 1
209 1 1
210 1 1
211 1 1
213 1 1
215 1 1
216 1 1
218 1 1
220 1 1
222 1 1
223 1 1
225 1 1
227 1 1
232 1 1
233 1 1
235 1 1
236 1 1
237 1 1
239 1 1
244 1 1
245 1 1
247 1 1
249 1 1
250 1 1
252 1 1
253 1 1
254 1 1
256 1 1
258 1 1
263 1 1
264 1 1
266 1 1
271 1 1
276 1 1
277 1 1
289 1 1
290 1 1
MISSING_ELSE
300 1 1
301 1 1
302 1 1
317 1 1
319 1 1
321 1 1
323 1 1
MISSING_ELSE
332 1 1
334 1 1
MISSING_ELSE
343 1 1
344 0 1
MISSING_ELSE
353 1 1
355 1 1
MISSING_ELSE
364 1 1
366 0 1
MISSING_ELSE


Cond Coverage for Module : sha3
TotalCoveredPercent
Conditions161381.25
Logical161381.25
Non-Logical00
Event00

 LINE       131
 EXPRESSION (round_count_error | msg_count_error)
             --------1--------   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T6
10CoveredT4,T5,T6

 LINE       137
 EXPRESSION (sha3_state_error | keccak_round_state_error | sha3pad_state_error)
             --------1-------   ------------2-----------   ---------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT4,T5,T6
010CoveredT4,T5,T6
100CoveredT4,T5,T6

 LINE       159
 EXPRESSION (sha3pad_keccak_run | sw_keccak_run)
             ---------1--------   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       232
 EXPRESSION (process_i && ((!processing)))
             ----1----    -------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       343
 EXPRESSION (start_i || process_i)
             ---1---    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

FSM Coverage for Module : sha3
Summary for FSM :: st
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 11 9 81.82
Sequences 0 0

State, Transition and Sequence Details for FSM :: st
statesLine No.CoveredTests
StAbsorb_sparse 223 Covered T1,T2,T3
StFlush_sparse 254 Covered T1,T2,T3
StIdle_sparse 227 Covered T1,T2,T3
StManualRun_sparse 250 Covered T1,T2,T3
StSqueeze_sparse 237 Covered T1,T2,T3
StTerminalError_sparse 276 Covered T7,T8,T9


transitionsLine No.CoveredTests
StAbsorb_sparse->StSqueeze_sparse 237 Covered T1,T2,T3
StAbsorb_sparse->StTerminalError_sparse 290 Covered T7,T8,T9
StFlush_sparse->StIdle_sparse 271 Covered T1,T2,T3
StFlush_sparse->StTerminalError_sparse 290 Not Covered
StIdle_sparse->StAbsorb_sparse 223 Covered T1,T2,T3
StIdle_sparse->StTerminalError_sparse 290 Covered T4,T5,T10
StManualRun_sparse->StSqueeze_sparse 264 Covered T1,T2,T3
StManualRun_sparse->StTerminalError_sparse 290 Not Covered
StSqueeze_sparse->StFlush_sparse 254 Covered T1,T2,T3
StSqueeze_sparse->StManualRun_sparse 250 Covered T1,T2,T3
StSqueeze_sparse->StTerminalError_sparse 290 Covered T11,T12,T13



Branch Coverage for Module : sha3
Line No.TotalCoveredPercent
Branches 37 34 91.89
IF 166 2 2 100.00
IF 175 4 4 100.00
IF 195 2 2 100.00
CASE 220 13 13 100.00
IF 289 2 2 100.00
CASE 300 3 2 66.67
CASE 319 11 9 81.82

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 166 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 175 if ((!rst_ni)) -2-: 176 if (process_i) -3-: 177 if (prim_mubi_pkg::mubi4_test_true_strict(absorbed))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 195 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 220 case (st) -2-: 222 if (start_i) -3-: 232 if ((process_i && (!processing))) -4-: 236 if (prim_mubi_pkg::mubi4_test_true_strict(absorbed)) -5-: 249 if (run_i) -6-: 253 if (prim_mubi_pkg::mubi4_test_true_strict(done_i)) -7-: 263 if (keccak_complete)

Branches:
-1--2--3--4--5--6--7-StatusTests
StIdle_sparse 1 - - - - - Covered T1,T2,T3
StIdle_sparse 0 - - - - - Covered T1,T2,T3
StAbsorb_sparse - 1 - - - - Covered T1,T2,T3
StAbsorb_sparse - 0 1 - - - Covered T1,T2,T3
StAbsorb_sparse - 0 0 - - - Covered T1,T2,T3
StSqueeze_sparse - - - 1 - - Covered T1,T2,T3
StSqueeze_sparse - - - 0 1 - Covered T1,T2,T3
StSqueeze_sparse - - - 0 0 - Covered T1,T2,T3
StManualRun_sparse - - - - - 1 Covered T1,T2,T3
StManualRun_sparse - - - - - 0 Covered T1,T2,T3
StFlush_sparse - - - - - - Covered T1,T2,T3
StTerminalError_sparse - - - - - - Covered T7,T8,T9
default - - - - - - Covered T4,T5,T6


LineNo. Expression -1-: 289 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 300 case (mux_sel)

Branches:
-1-StatusTests
MuxGuard Covered T1,T2,T3
MuxRelease Covered T1,T2,T3
default Not Covered


LineNo. Expression -1-: 319 case (st) -2-: 321 if (((process_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i))) -3-: 332 if ((((start_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)) || (process_i && processing))) -4-: 343 if ((start_i || process_i)) -5-: 353 if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i))) -6-: 364 if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))

Branches:
-1--2--3--4--5--6-StatusTests
StIdle_sparse 1 - - - - Covered T14,T15,T16
StIdle_sparse 0 - - - - Covered T1,T2,T3
StAbsorb_sparse - 1 - - - Covered T14,T15,T16
StAbsorb_sparse - 0 - - - Covered T1,T2,T3
StSqueeze_sparse - - 1 - - Not Covered
StSqueeze_sparse - - 0 - - Covered T1,T2,T3
StManualRun_sparse - - - 1 - Covered T14,T15,T16
StManualRun_sparse - - - 0 - Covered T1,T2,T3
StFlush_sparse - - - - 1 Not Covered
StFlush_sparse - - - - 0 Covered T1,T2,T3
default - - - - - Covered T7,T8,T9


Assert Coverage for Module : sha3
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ErrDetection_A 2147483647 9843328 0 0
FsmKnown_A 2147483647 2147483647 0 0
MuxSelKnown_A 2147483647 2147483647 0 0
SwRunInSqueezing_a 2147483647 155870 0 0
gen_chk_digest_masked.StateZeroInvalid_A 2147483647 2147483647 0 0
u_state_regs_A 2147483647 2147483647 0 0


ErrDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 9843328 0 0
T14 195327 128385 0 0
T15 0 180930 0 0
T16 0 68869 0 0
T17 0 256651 0 0
T18 0 103164 0 0
T19 0 167382 0 0
T20 0 16719 0 0
T21 0 393566 0 0
T22 0 14456 0 0
T23 0 16739 0 0
T24 605080 0 0 0
T25 516650 0 0 0
T26 113887 0 0 0
T27 662685 0 0 0
T28 101191 0 0 0
T29 563235 0 0 0
T30 514612 0 0 0
T31 377289 0 0 0
T32 605297 0 0 0

FsmKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 533129 533124 0 0
T2 131538 131444 0 0
T3 168194 168127 0 0
T7 3239 3096 0 0
T33 41148 41064 0 0
T34 148803 148719 0 0
T35 625402 625397 0 0
T36 140629 140621 0 0
T37 762290 762230 0 0
T38 626306 626301 0 0

MuxSelKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 533129 533124 0 0
T2 131538 131444 0 0
T3 168194 168127 0 0
T7 3239 3096 0 0
T33 41148 41064 0 0
T34 148803 148719 0 0
T35 625402 625397 0 0
T36 140629 140621 0 0
T37 762290 762230 0 0
T38 626306 626301 0 0

SwRunInSqueezing_a
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 155870 0 0
T1 533129 571 0 0
T2 131538 95 0 0
T3 168194 79 0 0
T7 3239 0 0 0
T33 41148 44 0 0
T34 148803 28 0 0
T35 625402 0 0 0
T36 140629 433 0 0
T37 762290 177 0 0
T38 626306 0 0 0
T39 0 415 0 0
T40 0 141 0 0
T41 0 139 0 0

gen_chk_digest_masked.StateZeroInvalid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 533129 407189 0 0
T2 131538 103440 0 0
T3 168194 106125 0 0
T7 3239 3096 0 0
T33 41148 27508 0 0
T34 148803 123958 0 0
T35 625402 483834 0 0
T36 140629 102826 0 0
T37 762290 702566 0 0
T38 626306 597531 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 533129 533124 0 0
T2 131538 131444 0 0
T3 168194 168127 0 0
T7 3239 3096 0 0
T33 41148 41064 0 0
T34 148803 148719 0 0
T35 625402 625397 0 0
T36 140629 140621 0 0
T37 762290 762230 0 0
T38 626306 626301 0 0

Line Coverage for Instance : tb.dut.u_sha3
Line No.TotalCoveredPercent
TOTAL747297.30
CONT_ASSIGN13111100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN15911100.00
ALWAYS16633100.00
CONT_ASSIGN17111100.00
ALWAYS17566100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18511100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18811100.00
ALWAYS19533100.00
ALWAYS2053838100.00
ALWAYS30033100.00
ALWAYS317121083.33
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
131 1 1
137 1 1
141 1 1
159 1 1
166 2 2
167 1 1
171 1 1
175 2 2
176 2 2
177 1 1
178 1 1
MISSING_ELSE
182 1 1
185 1 1
186 1 1
188 1 1
195 3 3
205 1 1
208 1 1
209 1 1
210 1 1
211 1 1
213 1 1
215 1 1
216 1 1
218 1 1
220 1 1
222 1 1
223 1 1
225 1 1
227 1 1
232 1 1
233 1 1
235 1 1
236 1 1
237 1 1
239 1 1
244 1 1
245 1 1
247 1 1
249 1 1
250 1 1
252 1 1
253 1 1
254 1 1
256 1 1
258 1 1
263 1 1
264 1 1
266 1 1
271 1 1
276 1 1
277 1 1
289 1 1
290 1 1
MISSING_ELSE
300 1 1
301 1 1
302 1 1
317 1 1
319 1 1
321 1 1
323 1 1
MISSING_ELSE
332 1 1
334 1 1
MISSING_ELSE
343 1 1
344 0 1
MISSING_ELSE
353 1 1
355 1 1
MISSING_ELSE
364 1 1
366 0 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_sha3
TotalCoveredPercent
Conditions161381.25
Logical161381.25
Non-Logical00
Event00

 LINE       131
 EXPRESSION (round_count_error | msg_count_error)
             --------1--------   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T6
10CoveredT4,T5,T6

 LINE       137
 EXPRESSION (sha3_state_error | keccak_round_state_error | sha3pad_state_error)
             --------1-------   ------------2-----------   ---------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT4,T5,T6
010CoveredT4,T5,T6
100CoveredT4,T5,T6

 LINE       159
 EXPRESSION (sha3pad_keccak_run | sw_keccak_run)
             ---------1--------   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       232
 EXPRESSION (process_i && ((!processing)))
             ----1----    -------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       343
 EXPRESSION (start_i || process_i)
             ---1---    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

FSM Coverage for Instance : tb.dut.u_sha3
Summary for FSM :: st
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 9 9 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: st
statesLine No.CoveredTests
StAbsorb_sparse 223 Covered T1,T2,T3
StFlush_sparse 254 Covered T1,T2,T3
StIdle_sparse 227 Covered T1,T2,T3
StManualRun_sparse 250 Covered T1,T2,T3
StSqueeze_sparse 237 Covered T1,T2,T3
StTerminalError_sparse 276 Covered T7,T8,T9


transitionsLine No.CoveredTestsExclude Annotation
StAbsorb_sparse->StSqueeze_sparse 237 Covered T1,T2,T3
StAbsorb_sparse->StTerminalError_sparse 290 Covered T7,T8,T9
StFlush_sparse->StIdle_sparse 271 Covered T1,T2,T3
StFlush_sparse->StTerminalError_sparse 290 Excluded [LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StIdle_sparse->StAbsorb_sparse 223 Covered T1,T2,T3
StIdle_sparse->StTerminalError_sparse 290 Covered T4,T5,T10
StManualRun_sparse->StSqueeze_sparse 264 Covered T1,T2,T3
StManualRun_sparse->StTerminalError_sparse 290 Excluded [LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StSqueeze_sparse->StFlush_sparse 254 Covered T1,T2,T3
StSqueeze_sparse->StManualRun_sparse 250 Covered T1,T2,T3
StSqueeze_sparse->StTerminalError_sparse 290 Covered T11,T12,T13



Branch Coverage for Instance : tb.dut.u_sha3
Line No.TotalCoveredPercent
Branches 37 34 91.89
IF 166 2 2 100.00
IF 175 4 4 100.00
IF 195 2 2 100.00
CASE 220 13 13 100.00
IF 289 2 2 100.00
CASE 300 3 2 66.67
CASE 319 11 9 81.82

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 166 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 175 if ((!rst_ni)) -2-: 176 if (process_i) -3-: 177 if (prim_mubi_pkg::mubi4_test_true_strict(absorbed))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 195 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 220 case (st) -2-: 222 if (start_i) -3-: 232 if ((process_i && (!processing))) -4-: 236 if (prim_mubi_pkg::mubi4_test_true_strict(absorbed)) -5-: 249 if (run_i) -6-: 253 if (prim_mubi_pkg::mubi4_test_true_strict(done_i)) -7-: 263 if (keccak_complete)

Branches:
-1--2--3--4--5--6--7-StatusTests
StIdle_sparse 1 - - - - - Covered T1,T2,T3
StIdle_sparse 0 - - - - - Covered T1,T2,T3
StAbsorb_sparse - 1 - - - - Covered T1,T2,T3
StAbsorb_sparse - 0 1 - - - Covered T1,T2,T3
StAbsorb_sparse - 0 0 - - - Covered T1,T2,T3
StSqueeze_sparse - - - 1 - - Covered T1,T2,T3
StSqueeze_sparse - - - 0 1 - Covered T1,T2,T3
StSqueeze_sparse - - - 0 0 - Covered T1,T2,T3
StManualRun_sparse - - - - - 1 Covered T1,T2,T3
StManualRun_sparse - - - - - 0 Covered T1,T2,T3
StFlush_sparse - - - - - - Covered T1,T2,T3
StTerminalError_sparse - - - - - - Covered T7,T8,T9
default - - - - - - Covered T4,T5,T6


LineNo. Expression -1-: 289 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 300 case (mux_sel)

Branches:
-1-StatusTests
MuxGuard Covered T1,T2,T3
MuxRelease Covered T1,T2,T3
default Not Covered


LineNo. Expression -1-: 319 case (st) -2-: 321 if (((process_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i))) -3-: 332 if ((((start_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)) || (process_i && processing))) -4-: 343 if ((start_i || process_i)) -5-: 353 if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i))) -6-: 364 if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))

Branches:
-1--2--3--4--5--6-StatusTests
StIdle_sparse 1 - - - - Covered T14,T15,T16
StIdle_sparse 0 - - - - Covered T1,T2,T3
StAbsorb_sparse - 1 - - - Covered T14,T15,T16
StAbsorb_sparse - 0 - - - Covered T1,T2,T3
StSqueeze_sparse - - 1 - - Not Covered
StSqueeze_sparse - - 0 - - Covered T1,T2,T3
StManualRun_sparse - - - 1 - Covered T14,T15,T16
StManualRun_sparse - - - 0 - Covered T1,T2,T3
StFlush_sparse - - - - 1 Not Covered
StFlush_sparse - - - - 0 Covered T1,T2,T3
default - - - - - Covered T7,T8,T9


Assert Coverage for Instance : tb.dut.u_sha3
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ErrDetection_A 2147483647 9843328 0 0
FsmKnown_A 2147483647 2147483647 0 0
MuxSelKnown_A 2147483647 2147483647 0 0
SwRunInSqueezing_a 2147483647 155870 0 0
gen_chk_digest_masked.StateZeroInvalid_A 2147483647 2147483647 0 0
u_state_regs_A 2147483647 2147483647 0 0


ErrDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 9843328 0 0
T14 195327 128385 0 0
T15 0 180930 0 0
T16 0 68869 0 0
T17 0 256651 0 0
T18 0 103164 0 0
T19 0 167382 0 0
T20 0 16719 0 0
T21 0 393566 0 0
T22 0 14456 0 0
T23 0 16739 0 0
T24 605080 0 0 0
T25 516650 0 0 0
T26 113887 0 0 0
T27 662685 0 0 0
T28 101191 0 0 0
T29 563235 0 0 0
T30 514612 0 0 0
T31 377289 0 0 0
T32 605297 0 0 0

FsmKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 533129 533124 0 0
T2 131538 131444 0 0
T3 168194 168127 0 0
T7 3239 3096 0 0
T33 41148 41064 0 0
T34 148803 148719 0 0
T35 625402 625397 0 0
T36 140629 140621 0 0
T37 762290 762230 0 0
T38 626306 626301 0 0

MuxSelKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 533129 533124 0 0
T2 131538 131444 0 0
T3 168194 168127 0 0
T7 3239 3096 0 0
T33 41148 41064 0 0
T34 148803 148719 0 0
T35 625402 625397 0 0
T36 140629 140621 0 0
T37 762290 762230 0 0
T38 626306 626301 0 0

SwRunInSqueezing_a
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 155870 0 0
T1 533129 571 0 0
T2 131538 95 0 0
T3 168194 79 0 0
T7 3239 0 0 0
T33 41148 44 0 0
T34 148803 28 0 0
T35 625402 0 0 0
T36 140629 433 0 0
T37 762290 177 0 0
T38 626306 0 0 0
T39 0 415 0 0
T40 0 141 0 0
T41 0 139 0 0

gen_chk_digest_masked.StateZeroInvalid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 533129 407189 0 0
T2 131538 103440 0 0
T3 168194 106125 0 0
T7 3239 3096 0 0
T33 41148 27508 0 0
T34 148803 123958 0 0
T35 625402 483834 0 0
T36 140629 102826 0 0
T37 762290 702566 0 0
T38 626306 597531 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 533129 533124 0 0
T2 131538 131444 0 0
T3 168194 168127 0 0
T7 3239 3096 0 0
T33 41148 41064 0 0
T34 148803 148719 0 0
T35 625402 625397 0 0
T36 140629 140621 0 0
T37 762290 762230 0 0
T38 626306 626301 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%