Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	721926	0	0
entropy_period_rd_A	2147483647	1662	0	0
intr_enable_rd_A	2147483647	2349	0	0
prefix_0_rd_A	2147483647	1593	0	0
prefix_10_rd_A	2147483647	1562	0	0
prefix_1_rd_A	2147483647	1570	0	0
prefix_2_rd_A	2147483647	1575	0	0
prefix_3_rd_A	2147483647	1439	0	0
prefix_4_rd_A	2147483647	1606	0	0
prefix_5_rd_A	2147483647	1625	0	0
prefix_6_rd_A	2147483647	1529	0	0
prefix_7_rd_A	2147483647	1631	0	0
prefix_8_rd_A	2147483647	1456	0	0
prefix_9_rd_A	2147483647	1439	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	721926	0	0
T16	848602	78015	0	0
T17	940704	0	0	0
T22	0	59589	0	0
T23	0	41258	0	0
T56	117508	0	0	0
T60	759425	0	0	0
T114	38039	0	0	0
T140	0	57636	0	0
T141	0	114302	0	0
T142	0	85346	0	0
T143	0	40245	0	0
T144	0	41109	0	0
T145	0	20225	0	0
T146	0	77349	0	0
T147	841153	0	0	0
T148	102308	0	0	0
T149	365113	0	0	0
T150	161871	0	0	0
T151	101956	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1662	0	0
T22	637773	179	0	0
T23	293850	0	0	0
T50	3348	0	0	0
T87	0	58	0	0
T88	0	16	0	0
T98	0	72	0	0
T144	0	118	0	0
T160	0	74	0	0
T161	0	34	0	0
T162	0	9	0	0
T163	0	260	0	0
T164	0	46	0	0
T165	654501	0	0	0
T166	18797	0	0	0
T167	44467	0	0	0
T168	116005	0	0	0
T169	607155	0	0	0
T170	1596	0	0	0
T171	873603	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2349	0	0
T22	637773	178	0	0
T23	293850	0	0	0
T50	3348	0	0	0
T87	0	36	0	0
T88	0	21	0	0
T98	0	110	0	0
T137	0	11	0	0
T144	0	114	0	0
T160	0	40	0	0
T161	0	20	0	0
T162	0	12	0	0
T165	654501	0	0	0
T166	18797	0	0	0
T167	44467	0	0	0
T168	116005	0	0	0
T169	607155	0	0	0
T170	1596	0	0	0
T171	873603	0	0	0
T172	0	22	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1593	0	0
T22	637773	134	0	0
T23	293850	0	0	0
T50	3348	0	0	0
T87	0	26	0	0
T88	0	18	0	0
T98	0	95	0	0
T144	0	138	0	0
T160	0	80	0	0
T161	0	15	0	0
T162	0	11	0	0
T163	0	241	0	0
T164	0	53	0	0
T165	654501	0	0	0
T166	18797	0	0	0
T167	44467	0	0	0
T168	116005	0	0	0
T169	607155	0	0	0
T170	1596	0	0	0
T171	873603	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1562	0	0
T22	637773	163	0	0
T23	293850	0	0	0
T50	3348	0	0	0
T87	0	13	0	0
T88	0	18	0	0
T98	0	79	0	0
T144	0	97	0	0
T160	0	38	0	0
T161	0	14	0	0
T162	0	3	0	0
T163	0	239	0	0
T164	0	40	0	0
T165	654501	0	0	0
T166	18797	0	0	0
T167	44467	0	0	0
T168	116005	0	0	0
T169	607155	0	0	0
T170	1596	0	0	0
T171	873603	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1570	0	0
T22	637773	131	0	0
T23	293850	0	0	0
T50	3348	0	0	0
T87	0	23	0	0
T88	0	6	0	0
T98	0	67	0	0
T144	0	151	0	0
T160	0	44	0	0
T161	0	31	0	0
T162	0	12	0	0
T163	0	263	0	0
T164	0	51	0	0
T165	654501	0	0	0
T166	18797	0	0	0
T167	44467	0	0	0
T168	116005	0	0	0
T169	607155	0	0	0
T170	1596	0	0	0
T171	873603	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1575	0	0
T22	637773	129	0	0
T23	293850	0	0	0
T50	3348	0	0	0
T87	0	13	0	0
T88	0	19	0	0
T98	0	56	0	0
T144	0	136	0	0
T160	0	80	0	0
T161	0	5	0	0
T162	0	9	0	0
T163	0	238	0	0
T164	0	39	0	0
T165	654501	0	0	0
T166	18797	0	0	0
T167	44467	0	0	0
T168	116005	0	0	0
T169	607155	0	0	0
T170	1596	0	0	0
T171	873603	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1439	0	0
T22	637773	109	0	0
T23	293850	0	0	0
T50	3348	0	0	0
T87	0	21	0	0
T88	0	13	0	0
T98	0	50	0	0
T144	0	106	0	0
T160	0	22	0	0
T161	0	21	0	0
T162	0	2	0	0
T163	0	205	0	0
T164	0	59	0	0
T165	654501	0	0	0
T166	18797	0	0	0
T167	44467	0	0	0
T168	116005	0	0	0
T169	607155	0	0	0
T170	1596	0	0	0
T171	873603	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1606	0	0
T22	637773	151	0	0
T23	293850	0	0	0
T50	3348	0	0	0
T87	0	31	0	0
T88	0	17	0	0
T98	0	62	0	0
T144	0	140	0	0
T160	0	26	0	0
T161	0	9	0	0
T162	0	9	0	0
T163	0	273	0	0
T164	0	67	0	0
T165	654501	0	0	0
T166	18797	0	0	0
T167	44467	0	0	0
T168	116005	0	0	0
T169	607155	0	0	0
T170	1596	0	0	0
T171	873603	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1625	0	0
T22	637773	132	0	0
T23	293850	0	0	0
T50	3348	0	0	0
T87	0	10	0	0
T88	0	27	0	0
T98	0	85	0	0
T144	0	121	0	0
T160	0	54	0	0
T161	0	21	0	0
T162	0	9	0	0
T163	0	236	0	0
T164	0	63	0	0
T165	654501	0	0	0
T166	18797	0	0	0
T167	44467	0	0	0
T168	116005	0	0	0
T169	607155	0	0	0
T170	1596	0	0	0
T171	873603	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1529	0	0
T22	637773	147	0	0
T23	293850	0	0	0
T50	3348	0	0	0
T87	0	16	0	0
T88	0	17	0	0
T98	0	61	0	0
T144	0	92	0	0
T160	0	21	0	0
T161	0	20	0	0
T162	0	5	0	0
T163	0	251	0	0
T164	0	15	0	0
T165	654501	0	0	0
T166	18797	0	0	0
T167	44467	0	0	0
T168	116005	0	0	0
T169	607155	0	0	0
T170	1596	0	0	0
T171	873603	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1631	0	0
T22	637773	129	0	0
T23	293850	0	0	0
T50	3348	0	0	0
T87	0	30	0	0
T88	0	27	0	0
T98	0	76	0	0
T144	0	134	0	0
T160	0	62	0	0
T161	0	18	0	0
T162	0	11	0	0
T163	0	248	0	0
T164	0	51	0	0
T165	654501	0	0	0
T166	18797	0	0	0
T167	44467	0	0	0
T168	116005	0	0	0
T169	607155	0	0	0
T170	1596	0	0	0
T171	873603	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1456	0	0
T22	637773	132	0	0
T23	293850	0	0	0
T50	3348	0	0	0
T87	0	16	0	0
T88	0	13	0	0
T98	0	51	0	0
T144	0	144	0	0
T160	0	20	0	0
T161	0	18	0	0
T162	0	8	0	0
T163	0	220	0	0
T164	0	21	0	0
T165	654501	0	0	0
T166	18797	0	0	0
T167	44467	0	0	0
T168	116005	0	0	0
T169	607155	0	0	0
T170	1596	0	0	0
T171	873603	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1439	0	0
T22	637773	113	0	0
T23	293850	0	0	0
T50	3348	0	0	0
T87	0	10	0	0
T88	0	13	0	0
T98	0	68	0	0
T144	0	165	0	0
T160	0	14	0	0
T161	0	12	0	0
T162	0	7	0	0
T163	0	248	0	0
T164	0	17	0	0
T165	654501	0	0	0
T166	18797	0	0	0
T167	44467	0	0	0
T168	116005	0	0	0
T169	607155	0	0	0
T170	1596	0	0	0
T171	873603	0	0	0