Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	573358	0	0
entropy_period_rd_A	2147483647	1519	0	0
intr_enable_rd_A	2147483647	2283	0	0
prefix_0_rd_A	2147483647	1802	0	0
prefix_10_rd_A	2147483647	1879	0	0
prefix_1_rd_A	2147483647	1878	0	0
prefix_2_rd_A	2147483647	1854	0	0
prefix_3_rd_A	2147483647	1882	0	0
prefix_4_rd_A	2147483647	1749	0	0
prefix_5_rd_A	2147483647	1798	0	0
prefix_6_rd_A	2147483647	1892	0	0
prefix_7_rd_A	2147483647	1897	0	0
prefix_8_rd_A	2147483647	1956	0	0
prefix_9_rd_A	2147483647	1934	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	573358	0	0
T13	2728	0	0	0
T27	167824	12831	0	0
T42	0	35558	0	0
T45	0	9245	0	0
T64	162332	0	0	0
T73	423499	26611	0	0
T77	140986	0	0	0
T105	74423	0	0	0
T125	0	74489	0	0
T126	0	33222	0	0
T127	0	72955	0	0
T128	0	30475	0	0
T129	0	37711	0	0
T130	0	54121	0	0
T131	150872	0	0	0
T132	26704	0	0	0
T133	613980	0	0	0
T134	105999	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1519	0	0
T13	2728	0	0	0
T27	167824	56	0	0
T64	162332	0	0	0
T73	423499	0	0	0
T77	140986	0	0	0
T105	74423	0	0	0
T124	0	38	0	0
T131	150872	0	0	0
T132	26704	0	0	0
T133	613980	0	0	0
T134	105999	0	0	0
T149	0	75	0	0
T150	0	37	0	0
T151	0	11	0	0
T152	0	2	0	0
T153	0	128	0	0
T154	0	16	0	0
T155	0	18	0	0
T156	0	11	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2283	0	0
T13	2728	0	0	0
T27	167824	36	0	0
T64	162332	0	0	0
T73	423499	0	0	0
T77	140986	0	0	0
T105	74423	0	0	0
T123	0	21	0	0
T124	0	59	0	0
T131	150872	0	0	0
T132	26704	0	0	0
T133	613980	0	0	0
T134	105999	0	0	0
T149	0	86	0	0
T150	0	36	0	0
T151	0	44	0	0
T152	0	8	0	0
T153	0	84	0	0
T154	0	9	0	0
T157	0	27	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1802	0	0
T13	2728	0	0	0
T27	167824	55	0	0
T64	162332	0	0	0
T73	423499	0	0	0
T77	140986	0	0	0
T105	74423	0	0	0
T124	0	33	0	0
T131	150872	0	0	0
T132	26704	0	0	0
T133	613980	0	0	0
T134	105999	0	0	0
T149	0	44	0	0
T150	0	38	0	0
T151	0	18	0	0
T152	0	5	0	0
T153	0	72	0	0
T154	0	1	0	0
T155	0	26	0	0
T156	0	2	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1879	0	0
T13	2728	0	0	0
T27	167824	48	0	0
T64	162332	0	0	0
T73	423499	0	0	0
T77	140986	0	0	0
T105	74423	0	0	0
T124	0	17	0	0
T131	150872	0	0	0
T132	26704	0	0	0
T133	613980	0	0	0
T134	105999	0	0	0
T149	0	77	0	0
T150	0	73	0	0
T151	0	8	0	0
T153	0	97	0	0
T154	0	2	0	0
T155	0	13	0	0
T156	0	4	0	0
T158	0	3	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1878	0	0
T13	2728	0	0	0
T27	167824	45	0	0
T64	162332	0	0	0
T73	423499	0	0	0
T77	140986	0	0	0
T105	74423	0	0	0
T124	0	28	0	0
T131	150872	0	0	0
T132	26704	0	0	0
T133	613980	0	0	0
T134	105999	0	0	0
T149	0	74	0	0
T150	0	65	0	0
T152	0	8	0	0
T153	0	105	0	0
T154	0	3	0	0
T155	0	11	0	0
T156	0	7	0	0
T159	0	1	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1854	0	0
T13	2728	0	0	0
T27	167824	44	0	0
T64	162332	0	0	0
T73	423499	0	0	0
T77	140986	0	0	0
T105	74423	0	0	0
T124	0	32	0	0
T131	150872	0	0	0
T132	26704	0	0	0
T133	613980	0	0	0
T134	105999	0	0	0
T149	0	53	0	0
T150	0	40	0	0
T151	0	29	0	0
T152	0	5	0	0
T153	0	65	0	0
T154	0	8	0	0
T155	0	26	0	0
T156	0	2	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1882	0	0
T13	2728	0	0	0
T27	167824	67	0	0
T64	162332	0	0	0
T73	423499	0	0	0
T77	140986	0	0	0
T105	74423	0	0	0
T124	0	33	0	0
T131	150872	0	0	0
T132	26704	0	0	0
T133	613980	0	0	0
T134	105999	0	0	0
T149	0	82	0	0
T150	0	37	0	0
T151	0	1	0	0
T152	0	6	0	0
T153	0	74	0	0
T154	0	11	0	0
T155	0	9	0	0
T156	0	3	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1749	0	0
T13	2728	0	0	0
T27	167824	48	0	0
T64	162332	0	0	0
T73	423499	0	0	0
T77	140986	0	0	0
T92	0	13	0	0
T105	74423	0	0	0
T124	0	36	0	0
T131	150872	0	0	0
T132	26704	0	0	0
T133	613980	0	0	0
T134	105999	0	0	0
T149	0	41	0	0
T150	0	64	0	0
T151	0	13	0	0
T152	0	2	0	0
T153	0	81	0	0
T154	0	3	0	0
T155	0	12	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1798	0	0
T13	2728	0	0	0
T27	167824	27	0	0
T64	162332	0	0	0
T73	423499	0	0	0
T77	140986	0	0	0
T105	74423	0	0	0
T124	0	37	0	0
T131	150872	0	0	0
T132	26704	0	0	0
T133	613980	0	0	0
T134	105999	0	0	0
T149	0	77	0	0
T150	0	14	0	0
T151	0	29	0	0
T152	0	7	0	0
T153	0	93	0	0
T154	0	10	0	0
T155	0	14	0	0
T156	0	1	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1892	0	0
T13	2728	0	0	0
T27	167824	51	0	0
T64	162332	0	0	0
T73	423499	0	0	0
T77	140986	0	0	0
T105	74423	0	0	0
T124	0	25	0	0
T131	150872	0	0	0
T132	26704	0	0	0
T133	613980	0	0	0
T134	105999	0	0	0
T149	0	48	0	0
T150	0	62	0	0
T151	0	34	0	0
T152	0	7	0	0
T153	0	64	0	0
T154	0	5	0	0
T155	0	18	0	0
T156	0	9	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1897	0	0
T13	2728	0	0	0
T27	167824	55	0	0
T64	162332	0	0	0
T73	423499	0	0	0
T77	140986	0	0	0
T105	74423	0	0	0
T124	0	28	0	0
T131	150872	0	0	0
T132	26704	0	0	0
T133	613980	0	0	0
T134	105999	0	0	0
T149	0	100	0	0
T150	0	35	0	0
T151	0	43	0	0
T152	0	3	0	0
T153	0	96	0	0
T154	0	2	0	0
T155	0	10	0	0
T156	0	10	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1956	0	0
T13	2728	0	0	0
T27	167824	41	0	0
T64	162332	0	0	0
T73	423499	0	0	0
T77	140986	0	0	0
T92	0	11	0	0
T105	74423	0	0	0
T124	0	47	0	0
T131	150872	0	0	0
T132	26704	0	0	0
T133	613980	0	0	0
T134	105999	0	0	0
T149	0	104	0	0
T150	0	69	0	0
T152	0	2	0	0
T153	0	82	0	0
T154	0	6	0	0
T155	0	20	0	0
T156	0	3	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1934	0	0
T13	2728	0	0	0
T27	167824	21	0	0
T64	162332	0	0	0
T73	423499	0	0	0
T77	140986	0	0	0
T105	74423	0	0	0
T124	0	26	0	0
T131	150872	0	0	0
T132	26704	0	0	0
T133	613980	0	0	0
T134	105999	0	0	0
T149	0	78	0	0
T150	0	55	0	0
T151	0	8	0	0
T152	0	3	0	0
T153	0	101	0	0
T154	0	5	0	0
T155	0	15	0	0
T156	0	1	0	0