Unified Coverage Report :: Module :: kmac

Module : kmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.56	98.77	96.05	100.00	100.00	96.55	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	98.56	98.77	96.05	100.00	100.00	96.55	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.56	98.77	96.05	100.00	100.00	96.55	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.82	98.38	93.14	99.93	94.55	96.04	98.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
gen_entropy.u_entropy	99.29	100.00	95.74	100.00	100.00	100.00	100.00
gen_entropy.u_prim_sync_reqack_data	95.83	100.00	83.33			100.00	100.00
intr_fifo_empty	93.75	100.00	75.00			100.00	100.00
intr_kmac_done	93.75	100.00	75.00			100.00	100.00
intr_kmac_err	93.75	100.00	75.00			100.00	100.00
kmac_csr_assert	100.00						100.00
sha3pad_assert_cov_if	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_app_intf	97.42	97.45	90.82		100.00	98.82	100.00
u_errchk	94.60	95.06	94.59		90.00	93.33	100.00
u_kmac_core	95.80	98.88	92.86	100.00	100.00	91.38	91.67
u_msgfifo	97.32	100.00	95.16	94.52	100.00	94.23	100.00
u_prim_lc_sync	100.00	100.00				100.00	100.00
u_reg	98.99	99.41	96.63	100.00		98.94	100.00
u_sha3	96.50	98.83	95.67	100.00	88.10	96.40	100.00
u_sha3_done_sender	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00
u_staterd	89.71	89.72	80.83			88.30	100.00
u_tlul_adapter_msgfifo	79.67	86.78	73.83			76.83	81.25

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : kmac

	Line No.	Total	Covered	Percent
TOTAL		163	161	98.77
ALWAYS	343	0	0
ALWAYS	343	2	2	100.00
ALWAYS	349	1	0	0.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
ALWAYS	426	9	9	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
ALWAYS	485	6	6	100.00
ALWAYS	498	6	6	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	542	1	1	100.00
CONT_ASSIGN	544	1	1	100.00
CONT_ASSIGN	545	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
ALWAYS	560	5	5	100.00
CONT_ASSIGN	570	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	589	1	1	100.00
ALWAYS	609	3	3	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	632	1	1	100.00
CONT_ASSIGN	637	1	1	100.00
ALWAYS	640	7	7	100.00
CONT_ASSIGN	676	1	1	100.00
CONT_ASSIGN	681	1	1	100.00
CONT_ASSIGN	688	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
ALWAYS	718	3	3	100.00
ALWAYS	722	28	28	100.00
ALWAYS	860	3	3	100.00
CONT_ASSIGN	868	1	1	100.00
CONT_ASSIGN	868	1	1	100.00
CONT_ASSIGN	939	1	1	100.00
CONT_ASSIGN	941	1	1	100.00
CONT_ASSIGN	971	1	1	100.00
CONT_ASSIGN	976	1	1	100.00
CONT_ASSIGN	977	1	1	100.00
CONT_ASSIGN	979	1	1	100.00
CONT_ASSIGN	982	0	0
ALWAYS	1100	0	0
ALWAYS	1100	2	2	100.00
CONT_ASSIGN	1186	1	1	100.00
CONT_ASSIGN	1326	1	1	100.00
CONT_ASSIGN	1340	1	1	100.00
CONT_ASSIGN	1347	1	1	100.00
CONT_ASSIGN	1352	1	1	100.00
ALWAYS	1358	6	5	83.33
CONT_ASSIGN	1367	1	1	100.00
CONT_ASSIGN	1369	1	1	100.00
ALWAYS	1381	4	4	100.00
CONT_ASSIGN	1387	1	1	100.00
ALWAYS	1410	4	4	100.00
ALWAYS	1420	3	3	100.00
CONT_ASSIGN	1431	1	1	100.00
CONT_ASSIGN	1435	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
343	1	1
344	1	1
349	0	1
418	1	1
419	1	1
423	1	1
426	1	1
427	1	1
428	1	1
429	1	1
431	1	1
433	1	1
437	1	1
441	1	1
445	1	1
461	1	1
462	1	1
463	1	1
466	1	1
470	1	1
471	1	1
475	1	1
478	1	1
485	1	1
486	1	1
487	1	1
488	1	1
489	1	1
490	1	1
			MISSING_ELSE
			MISSING_ELSE
498	1	1
499	1	1
500	1	1
501	1	1
502	1	1
503	1	1
			MISSING_ELSE
			MISSING_ELSE
515	1	1
522	1	1
525	1	1
526	1	1
527	1	1
530	5	5
531	5	5
534	1	1
536	1	1
538	1	1
542	1	1
544	1	1
545	1	1
548	1	1
549	1	1
552	1	1
560	1	1
561	1	1
562	1	1
563	1	1
565	1	1
570	1	1
577	1	1
578	1	1
579	1	1
589	1	1
609	2	2
610	1	1
613	1	1
632	1	1
637	1	1
640	1	1
642	1	1
647	1	1
651	1	1
655	1	1
659	1	1
663	1	1
676	1	1
681	1	1
688	1	1
698	1	1
718	3	3
722	1	1
724	1	1
725	1	1
727	1	1
729	1	1
731	1	1
732	1	1
735	1	1
738	1	1
744	1	1
745	1	1
747	1	1
752	1	1
753	1	1
754	1	1
756	1	1
762	1	1
767	1	1
768	1	1
770	1	1
772	1	1
778	1	1
779	1	1
781	1	1
787	1	1
788	1	1
800	1	1
801	1	1
			MISSING_ELSE
860	1	1
861	1	1
863	1	1
868	2	2
939	1	1
941	1	1
971	1	1
976	1	1
977	1	1
979	1	1
982		unreachable
1100	1	1
1101	1	1
1186	1	1
1326	1	1
1340	1	1
1347	1	1
1352	1	1
1358	1	1
1359	1	1
1360	1	1
1361	0	1
1362	1	1
1363	1	1
			MISSING_ELSE
1367	1	1
1369	1	1
1381	1	1
1382	1	1
1383	1	1
1384	1	1
			MISSING_ELSE
1387	1	1
1410	1	1
1411	1	1
1412	1	1
1414	1	1
			MISSING_ELSE
1420	1	1
1421	1	1
1424	1	1
1431	1	1
1435	1	1
1437	6	6

---

Cond Coverage for Module : kmac

	Total	Covered	Percent
Conditions	76	73	96.05
Logical	76	73	96.05
Non-Logical	0	0
Event	0	0

 LINE       423
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       461
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       462
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       463
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       475
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       527
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T30,T34,T40

 LINE       538
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T34,T61,T73

 LINE       542
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T48,T54
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       549
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T8
1	0	1	Covered	T3,T7,T8
1	1	0	Covered	T3,T7,T8
1	1	1	Covered	T3,T7,T8

 LINE       562
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T99,T100
1	1	Covered	T1,T2,T3

 LINE       562
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

 LINE       562
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T8
1	-	Covered	T1,T2,T3

 LINE       570
 EXPRESSION (reg2hw.cfg_shadowed.err_processed.q & reg2hw.cfg_shadowed.err_processed.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T48,T76
1	1	Covered	T2,T48,T76

 LINE       613
 EXPRESSION (((~msgfifo_empty_q)) & msgfifo_empty)
             ----------1---------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T3,T7,T8

 LINE       632
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T63,T64,T74
0	0	1	0	Covered	T76,T84,T79
0	1	0	0	Covered	T2,T48,T60
1	0	0	0	Covered	T30,T34,T40

 LINE       676
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T4,T5,T6
0	0	1	0	Covered	T4,T5,T6
0	1	0	0	Covered	T4,T5,T6
1	0	0	0	Covered	T4,T5,T6

 LINE       688
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T4,T5,T6
0	0	0	0	1	0	Covered	T4,T5,T6
0	0	0	1	0	0	Covered	T4,T5,T6
0	0	1	0	0	0	Covered	T4,T5,T6
0	1	0	0	0	0	Covered	T4,T5,T6
1	0	0	0	0	0	Covered	T4,T5,T6

 LINE       729
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       731
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T3,T7,T30
1	Covered	T8,T30,T32

 LINE       745
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T30,T34,T40
1	Covered	T8,T30,T32

 LINE       971
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Not Covered
1	1	Covered	T3,T7,T8

 LINE       1101
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       1340
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T49,T104
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T49,T104

 LINE       1340
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T49,T104
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T49,T104

 LINE       1369
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T4,T5,T6
0	0	1	0	0	Covered	T12,T13,T14
0	1	0	0	0	Covered	T4,T5,T6
1	0	0	0	0	Not Covered

---

Toggle Coverage for Module : kmac

	Total	Covered	Percent
Totals	71	71	100.00
Total Bits	6534	6534	100.00
Total Bits 0->1	3267	3267	100.00
Total Bits 1->0	3267	3267	100.00

Ports	71	71	100.00
Port Bits	6534	6534	100.00
Port Bits 0->1	3267	3267	100.00
Port Bits 1->0	3267	3267	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T30,T34,T40	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T30,T34,T40	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T30,T34,T40	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T8,T30,T32	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T7,T31	Yes	T3,T7,T31	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T7	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T3,T7	Yes	T2,T3,T7	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T27,T73,T42	Yes	T27,T73,T42	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T7	Yes	T2,T3,T7	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T7	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T49,T104	Yes	T1,T49,T104	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T49,T104	Yes	T1,T49,T104	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T49,T104	Yes	T1,T49,T104	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T49,T104	Yes	T1,T49,T104	OUTPUT
keymgr_key_i.key[0][0]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][1]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][2]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][4:3]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][7:5]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][9:8]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][10]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][11]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][12]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][14:13]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][20:15]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][22:21]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][24:23]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][25]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][27:26]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][31:28]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][32]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][34:33]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][35]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][36]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][37]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][40:38]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][41]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][42]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][43]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][44]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][45]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][46]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][49:47]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][50]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][51]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][52]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][53]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][57:54]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][64:58]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][65]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][66]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][69:67]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][71:70]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][72]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][74:73]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][76:75]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][77]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][79:78]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][80]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][81]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][82]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][83]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][86:84]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][88:87]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][90:89]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][91]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][92]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][93]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][97:94]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][100:98]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][102:101]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][104:103]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][105]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][106]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][107]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][108]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][109]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][110]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][112:111]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][114:113]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][115]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][118:116]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][119]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][120]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][123:121]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][129:124]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][131:130]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][132]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][134:133]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][135]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][136]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][137]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][138]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][142:139]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][144:143]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][146:145]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][147]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][148]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][150:149]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][151]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][155:152]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][157:156]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][159:158]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][160]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][161]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][163:162]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][167:164]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][168]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][169]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][171:170]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][175:172]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][176]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][178:177]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][179]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][182:180]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][185:183]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][188:186]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][190:189]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][194:191]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][195]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][197:196]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][201:198]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][205:202]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][207:206]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][208]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][210:209]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][215:211]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][221:216]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][225:222]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][226]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][229:227]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][230]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][231]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][233:232]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][236:234]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][237]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][240:238]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][242:241]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][245:243]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][247:246]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][251:248]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][253:252]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[0][255:254]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][0]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][1]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][7:2]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][9:8]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][10]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][12:11]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][14:13]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][15]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][18:16]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][21:19]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][24:22]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][26:25]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][28:27]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][29]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][32:30]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][34:33]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][36:35]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][40:37]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][41]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][48:42]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][49]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][50]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][51]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][52]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][54:53]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][56:55]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][57]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][58]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][59]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][62:60]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][63]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][66:64]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][67]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][69:68]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][72:70]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][73]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][74]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][75]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][77:76]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][79:78]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][81:80]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][83:82]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][84]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][86:85]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][89:87]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][92:90]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][94:93]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][95]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][96]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][101:97]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][102]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][103]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][108:104]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][111:109]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][117:112]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][118]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][123:119]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][125:124]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][127:126]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][128]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][130:129]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][131]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][136:132]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][137]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][140:138]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][143:141]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][149:144]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][152:150]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][154:153]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][155]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][157:156]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][158]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][159]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][160]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][161]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][162]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][165:163]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][166]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][170:167]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][174:171]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][175]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][176]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][179:177]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][183:180]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][184]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][189:185]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][191:190]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][192]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][197:193]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][198]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][201:199]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][202]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][203]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][204]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][206:205]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][208:207]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][210:209]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][212:211]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][213]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][215:214]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][218:216]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][219]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][221:220]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][224:222]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][225]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][228:226]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][229]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][230]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][231]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][233:232]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][234]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][236:235]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][237]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][238]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][239]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][240]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][242:241]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][245:243]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][246]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][247]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][248]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][252:249]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][254:253]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.key[1][255]	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
keymgr_key_i.valid	Yes	Yes	T30,T32,T34	Yes	T30,T32,T34	INPUT
app_i[0].last	Yes	Yes	T30,T34,T40	Yes	T30,T34,T40	INPUT
app_i[0].strb[7:0]	Yes	Yes	T30,T34,T40	Yes	T30,T34,T40	INPUT
app_i[0].data[63:0]	Yes	Yes	T2,T30,T34	Yes	T2,T30,T34	INPUT
app_i[0].valid	Yes	Yes	T2,T30,T34	Yes	T2,T30,T34	INPUT
app_i[1].last	Yes	Yes	T30,T34,T40	Yes	T30,T34,T40	INPUT
app_i[1].strb[7:0]	Yes	Yes	T34,T40,T61	Yes	T34,T40,T61	INPUT
app_i[1].data[63:0]	Yes	Yes	T30,T34,T40	Yes	T30,T34,T40	INPUT
app_i[1].valid	Yes	Yes	T30,T34,T40	Yes	T30,T34,T40	INPUT
app_i[2].last	Yes	Yes	T30,T34,T40	Yes	T30,T34,T40	INPUT
app_i[2].strb[7:0]	Yes	Yes	T34,T40,T61	Yes	T34,T40,T61	INPUT
app_i[2].data[63:0]	Yes	Yes	T30,T34,T40	Yes	T30,T34,T40	INPUT
app_i[2].valid	Yes	Yes	T30,T34,T40	Yes	T30,T34,T40	INPUT
app_o[0].error	Yes	Yes	T30,T34,T40	Yes	T30,T34,T40	OUTPUT
app_o[0].digest_share1[383:0]	Yes	Yes	T30,T34,T40	Yes	T30,T34,T40	OUTPUT
app_o[0].digest_share0[383:0]	Yes	Yes	T30,T34,T40	Yes	T30,T34,T40	OUTPUT
app_o[0].done	Yes	Yes	T30,T34,T40	Yes	T30,T34,T40	OUTPUT
app_o[0].ready	Yes	Yes	T2,T30,T34	Yes	T2,T30,T34	OUTPUT
app_o[1].error	Yes	Yes	T30,T34,T14	Yes	T30,T34,T14	OUTPUT
app_o[1].digest_share1[383:0]	Yes	Yes	T30,T34,T40	Yes	T30,T34,T40	OUTPUT
app_o[1].digest_share0[383:0]	Yes	Yes	T30,T34,T40	Yes	T30,T34,T40	OUTPUT
app_o[1].done	Yes	Yes	T30,T34,T40	Yes	T30,T34,T40	OUTPUT
app_o[1].ready	Yes	Yes	T30,T34,T40	Yes	T30,T34,T40	OUTPUT
app_o[2].error	Yes	Yes	T30,T34,T40	Yes	T30,T34,T40	OUTPUT
app_o[2].digest_share1[383:0]	Yes	Yes	T30,T34,T40	Yes	T30,T34,T40	OUTPUT
app_o[2].digest_share0[383:0]	Yes	Yes	T34,T40,T54	Yes	T34,T40,T54	OUTPUT
app_o[2].done	Yes	Yes	T30,T34,T40	Yes	T30,T34,T40	OUTPUT
app_o[2].ready	Yes	Yes	T30,T34,T40	Yes	T30,T34,T40	OUTPUT
entropy_o.edn_req	Yes	Yes	T2,T30,T32	Yes	T2,T30,T32	OUTPUT
entropy_i.edn_bus[31:0]	Yes	Yes	T2,T30,T32	Yes	T2,T30,T32	INPUT
entropy_i.edn_fips	Yes	Yes	T30,T32,T34	Yes	T2,T30,T32	INPUT
entropy_i.edn_ack	Yes	Yes	T2,T30,T32	Yes	T2,T30,T32	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	INPUT
intr_kmac_done_o	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	OUTPUT
intr_fifo_empty_o	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	OUTPUT
intr_kmac_err_o	Yes	Yes	T2,T30,T34	Yes	T2,T30,T34	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : kmac

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	770	Covered	T3,T7,T8
KmacIdle	738	Covered	T1,T2,T3
KmacKeyBlock	745	Covered	T8,T30,T32
KmacMsgFeed	735	Covered	T3,T7,T8
KmacPrefix	732	Covered	T8,T30,T32
KmacTerminalError	787	Covered	T12,T13,T14

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	779	Covered	T3,T7,T8
KmacDigest->KmacTerminalError	801	Covered	T23,T36,T37
KmacIdle->KmacMsgFeed	735	Covered	T3,T7,T30
KmacIdle->KmacPrefix	732	Covered	T8,T30,T32
KmacIdle->KmacTerminalError	801	Covered	T4,T5,T6
KmacKeyBlock->KmacMsgFeed	754	Covered	T8,T30,T32
KmacKeyBlock->KmacTerminalError	801	Covered	T22,T70,T19
KmacMsgFeed->KmacDigest	770	Covered	T3,T7,T8
KmacMsgFeed->KmacIdle	767	Covered	T30,T34,T40
KmacMsgFeed->KmacTerminalError	801	Covered	T14,T16,T69
KmacPrefix->KmacKeyBlock	745	Covered	T8,T30,T32
KmacPrefix->KmacMsgFeed	745	Covered	T30,T34,T40
KmacPrefix->KmacTerminalError	801	Covered	T12,T13,T15

---

Branch Coverage for Module : kmac

	Line No.	Total	Covered	Percent
Branches		58	56	96.55
TERNARY	423	2	2	100.00
CASE	431	6	5	83.33
IF	485	3	3	100.00
IF	560	3	3	100.00
IF	609	2	2	100.00
CASE	642	6	6	100.00
IF	718	2	2	100.00
CASE	727	15	15	100.00
IF	800	2	2	100.00
TERNARY	1101	2	2	100.00
IF	1358	4	3	75.00
IF	1381	3	3	100.00
IF	1410	3	3	100.00
IF	1420	2	2	100.00
IF	498	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	423	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	431	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Covered	T3,T7,T8
CmdProcess	Covered	T3,T7,T8
CmdManualRun	Covered	T3,T7,T30
CmdDone	Covered	T3,T7,T8
CmdNone	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	485	if ((!rst_ni))
-2-:	487	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T3,T7,T8

	LineNo.	Expression
-1-:	560	if ((!rst_ni))
-2-:	562	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T3,T7,T8

	LineNo.	Expression
-1-:	609	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	642	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Covered	T2,T48,T60
errchecker_err.valid	Covered	T63,T64,T74
sha3_err.valid	Covered	T30,T34,T40
entropy_err.valid	Covered	T76,T84,T79
msgfifo_err.valid	Covered	T4,T5,T6
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	718	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	727	case (kmac_st)
-2-:	729	if ((kmac_cmd == CmdStart))
-3-:	731	if ((CShake == app_sha3_mode))
-4-:	744	if (sha3_block_processed)
-5-:	745	(app_kmac_en) ? 
-6-:	753	if (sha3_block_processed)
-7-:	762	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	768	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	778	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T8,T30,T32
KmacIdle	1	0	-	-	-	-	-	-	Covered	T3,T7,T30
KmacIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T8,T30,T32
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T30,T34,T40
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T8,T30,T32
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T8,T30,T32
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T8,T30,T32
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T30,T34,T40
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T3,T7,T8
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T3,T7,T8
KmacDigest	-	-	-	-	-	-	-	1	Covered	T3,T7,T8
KmacDigest	-	-	-	-	-	-	-	0	Covered	T3,T7,T8
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	800	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1101	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1358	if ((!rst_ni))
-2-:	1360	if (alert_recov_operation)
-3-:	1362	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T2,T48,T76
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1381	if ((!rst_ni))
-2-:	1383	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1410	if ((!rst_ni))
-2-:	1412	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1420	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	498	if ((!rst_ni))
-2-:	500	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T3,T7,T8

---

Assert Coverage for Module : kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	2147483647	2147483647	0	0
CmdSparse_M	2147483647	1281549	0	0
EnMaskingKnown_A	2147483647	2147483647	0	0
EntropyReadyLatched_A	2147483647	338377	0	0
EntrySizeRegSameToEntrySizePkg_A	1027	1027	0	0
ErrProcessedLatched_A	2147483647	821	0	0
FifoEmpty_A	2147483647	2147483647	0	0
FpvSecCmErrorCheckFsmCheck_A	2147483647	90	0	0
FpvSecCmKeccackFsmCheck_A	2147483647	90	0	0
FpvSecCmKeyIndexCountCheck_A	2147483647	90	0	0
FpvSecCmKmacAppFsmCheck_A	2147483647	90	0	0
FpvSecCmKmacCoreFsmCheck_A	2147483647	90	0	0
FpvSecCmKmacFsmCheck_A	2147483647	90	0	0
FpvSecCmRegWeOnehotCheck_A	2147483647	90	0	0
FpvSecCmRoundCountCheck_A	2147483647	90	0	0
FpvSecCmSHA3FsmCheck_A	2147483647	90	0	0
FpvSecCmSHA3padFsmCheck_A	2147483647	90	0	0
FpvSecCmSentMsgCountCheck_A	2147483647	90	0	0
KmacCmd_A	2147483647	2147483647	0	0
KmacDone_A	2147483647	2147483647	0	0
KmacErr_A	2147483647	2147483647	0	0
KmacStKnown_A	2147483647	2147483647	0	0
NumAlerts2_A	1027	1027	0	0
NumEntriesRegSameToNumEntriesPkg_A	1027	1027	0	0
PrefixRegSameToPrefixPkg_A	1027	1027	0	0
SecretKeyDivideBy32_A	1027	1027	0	0
Sha3AbsorbedPulse_A	2147483647	347162	0	0
TlOAReadyKnown_A	2147483647	2147483647	0	0
TlODValidKnown_A	2147483647	2147483647	0	0
g_testassertion.FpvSecCmEntropyFsmCheck_A	2147483647	90	0	0
g_testassertion.FpvSecCmHashCountCheck_A	2147483647	90	0	0
g_testassertion.FpvSecCmMsgFifoRptrCheck_A	2147483647	90	0	0
g_testassertion.FpvSecCmMsgFifoWptrCheck_A	2147483647	90	0	0
g_testassertion.FpvSecCmPackerCountCheck_A	2147483647	90	0	0
g_testassertion.FpvSecCmSeedIdxCountCheck_A	2147483647	90	0	0
u_state_regs_A	2147483647	2147483647	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2280	2193	0	0
T2	91200	91132	0	0
T3	541845	541839	0	0
T7	525101	525092	0	0
T8	24341	24267	0	0
T30	459864	459813	0	0
T31	131959	131958	0	0
T32	196932	196874	0	0
T33	657340	657332	0	0
T34	739155	739091	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1281549	0	0
T2	91200	3	0	0
T3	541845	7917	0	0
T7	525101	7919	0	0
T8	24341	29	0	0
T30	459864	1782	0	0
T31	131959	7443	0	0
T32	196932	375	0	0
T33	657340	1239	0	0
T34	739155	2549	0	0
T35	36904	28	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2280	2193	0	0
T2	91200	91132	0	0
T3	541845	541839	0	0
T7	525101	525092	0	0
T8	24341	24267	0	0
T30	459864	459813	0	0
T31	131959	131958	0	0
T32	196932	196874	0	0
T33	657340	657332	0	0
T34	739155	739091	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	338377	0	0
T2	91200	16	0	0
T3	541845	2173	0	0
T7	525101	2194	0	0
T8	24341	9	0	0
T30	459864	276	0	0
T31	131959	2263	0	0
T32	196932	115	0	0
T33	657340	382	0	0
T34	739155	454	0	0
T35	36904	9	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	821	0	0
T2	91200	16	0	0
T3	541845	0	0	0
T7	525101	0	0	0
T8	24341	0	0	0
T30	459864	0	0	0
T31	131959	0	0	0
T32	196932	0	0	0
T33	657340	0	0	0
T34	739155	0	0	0
T35	36904	0	0	0
T48	0	10	0	0
T55	0	13	0	0
T60	0	7	0	0
T68	0	5	0	0
T76	0	19	0	0
T105	0	12	0	0
T106	0	2	0	0
T107	0	2	0	0
T108	0	8	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2280	2193	0	0
T2	91200	91132	0	0
T3	541845	541839	0	0
T7	525101	525092	0	0
T8	24341	24267	0	0
T30	459864	459813	0	0
T31	131959	131958	0	0
T32	196932	196874	0	0
T33	657340	657332	0	0
T34	739155	739091	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T4	474987	20	0	0
T5	0	10	0	0
T6	0	20	0	0
T99	0	20	0	0
T100	0	20	0	0
T109	805609	0	0	0
T110	499901	0	0	0
T111	334537	0	0	0
T112	2489	0	0	0
T113	652240	0	0	0
T114	521904	0	0	0
T115	9483	0	0	0
T116	184460	0	0	0
T117	335566	0	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T4	474987	20	0	0
T5	0	10	0	0
T6	0	20	0	0
T99	0	20	0	0
T100	0	20	0	0
T109	805609	0	0	0
T110	499901	0	0	0
T111	334537	0	0	0
T112	2489	0	0	0
T113	652240	0	0	0
T114	521904	0	0	0
T115	9483	0	0	0
T116	184460	0	0	0
T117	335566	0	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T4	474987	20	0	0
T5	0	10	0	0
T6	0	20	0	0
T99	0	20	0	0
T100	0	20	0	0
T109	805609	0	0	0
T110	499901	0	0	0
T111	334537	0	0	0
T112	2489	0	0	0
T113	652240	0	0	0
T114	521904	0	0	0
T115	9483	0	0	0
T116	184460	0	0	0
T117	335566	0	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T4	474987	20	0	0
T5	0	10	0	0
T6	0	20	0	0
T99	0	20	0	0
T100	0	20	0	0
T109	805609	0	0	0
T110	499901	0	0	0
T111	334537	0	0	0
T112	2489	0	0	0
T113	652240	0	0	0
T114	521904	0	0	0
T115	9483	0	0	0
T116	184460	0	0	0
T117	335566	0	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T4	474987	20	0	0
T5	0	10	0	0
T6	0	20	0	0
T99	0	20	0	0
T100	0	20	0	0
T109	805609	0	0	0
T110	499901	0	0	0
T111	334537	0	0	0
T112	2489	0	0	0
T113	652240	0	0	0
T114	521904	0	0	0
T115	9483	0	0	0
T116	184460	0	0	0
T117	335566	0	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T4	474987	20	0	0
T5	0	10	0	0
T6	0	20	0	0
T99	0	20	0	0
T100	0	20	0	0
T109	805609	0	0	0
T110	499901	0	0	0
T111	334537	0	0	0
T112	2489	0	0	0
T113	652240	0	0	0
T114	521904	0	0	0
T115	9483	0	0	0
T116	184460	0	0	0
T117	335566	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T4	474987	20	0	0
T5	0	10	0	0
T6	0	20	0	0
T99	0	20	0	0
T100	0	20	0	0
T109	805609	0	0	0
T110	499901	0	0	0
T111	334537	0	0	0
T112	2489	0	0	0
T113	652240	0	0	0
T114	521904	0	0	0
T115	9483	0	0	0
T116	184460	0	0	0
T117	335566	0	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T4	474987	20	0	0
T5	0	10	0	0
T6	0	20	0	0
T99	0	20	0	0
T100	0	20	0	0
T109	805609	0	0	0
T110	499901	0	0	0
T111	334537	0	0	0
T112	2489	0	0	0
T113	652240	0	0	0
T114	521904	0	0	0
T115	9483	0	0	0
T116	184460	0	0	0
T117	335566	0	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T4	474987	20	0	0
T5	0	10	0	0
T6	0	20	0	0
T99	0	20	0	0
T100	0	20	0	0
T109	805609	0	0	0
T110	499901	0	0	0
T111	334537	0	0	0
T112	2489	0	0	0
T113	652240	0	0	0
T114	521904	0	0	0
T115	9483	0	0	0
T116	184460	0	0	0
T117	335566	0	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T4	474987	20	0	0
T5	0	10	0	0
T6	0	20	0	0
T99	0	20	0	0
T100	0	20	0	0
T109	805609	0	0	0
T110	499901	0	0	0
T111	334537	0	0	0
T112	2489	0	0	0
T113	652240	0	0	0
T114	521904	0	0	0
T115	9483	0	0	0
T116	184460	0	0	0
T117	335566	0	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T4	474987	20	0	0
T5	0	10	0	0
T6	0	20	0	0
T99	0	20	0	0
T100	0	20	0	0
T109	805609	0	0	0
T110	499901	0	0	0
T111	334537	0	0	0
T112	2489	0	0	0
T113	652240	0	0	0
T114	521904	0	0	0
T115	9483	0	0	0
T116	184460	0	0	0
T117	335566	0	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2280	2193	0	0
T2	91200	91132	0	0
T3	541845	541839	0	0
T7	525101	525092	0	0
T8	24341	24267	0	0
T30	459864	459813	0	0
T31	131959	131958	0	0
T32	196932	196874	0	0
T33	657340	657332	0	0
T34	739155	739091	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2280	2193	0	0
T2	91200	91132	0	0
T3	541845	541839	0	0
T7	525101	525092	0	0
T8	24341	24267	0	0
T30	459864	459813	0	0
T31	131959	131958	0	0
T32	196932	196874	0	0
T33	657340	657332	0	0
T34	739155	739091	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2280	2193	0	0
T2	91200	91132	0	0
T3	541845	541839	0	0
T7	525101	525092	0	0
T8	24341	24267	0	0
T30	459864	459813	0	0
T31	131959	131958	0	0
T32	196932	196874	0	0
T33	657340	657332	0	0
T34	739155	739091	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2280	2193	0	0
T2	91200	91132	0	0
T3	541845	541839	0	0
T7	525101	525092	0	0
T8	24341	24267	0	0
T30	459864	459813	0	0
T31	131959	131958	0	0
T32	196932	196874	0	0
T33	657340	657332	0	0
T34	739155	739091	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347162	0	0
T3	541845	2265	0	0
T7	525101	2265	0	0
T8	24341	9	0	0
T9	544769	390	0	0
T30	459864	279	0	0
T31	131959	2337	0	0
T32	196932	116	0	0
T33	657340	390	0	0
T34	739155	456	0	0
T35	36904	9	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2280	2193	0	0
T2	91200	91132	0	0
T3	541845	541839	0	0
T7	525101	525092	0	0
T8	24341	24267	0	0
T30	459864	459813	0	0
T31	131959	131958	0	0
T32	196932	196874	0	0
T33	657340	657332	0	0
T34	739155	739091	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2280	2193	0	0
T2	91200	91132	0	0
T3	541845	541839	0	0
T7	525101	525092	0	0
T8	24341	24267	0	0
T30	459864	459813	0	0
T31	131959	131958	0	0
T32	196932	196874	0	0
T33	657340	657332	0	0
T34	739155	739091	0	0

g_testassertion.FpvSecCmEntropyFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T4	474987	20	0	0
T5	0	10	0	0
T6	0	20	0	0
T99	0	20	0	0
T100	0	20	0	0
T109	805609	0	0	0
T110	499901	0	0	0
T111	334537	0	0	0
T112	2489	0	0	0
T113	652240	0	0	0
T114	521904	0	0	0
T115	9483	0	0	0
T116	184460	0	0	0
T117	335566	0	0	0

g_testassertion.FpvSecCmHashCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T4	474987	20	0	0
T5	0	10	0	0
T6	0	20	0	0
T99	0	20	0	0
T100	0	20	0	0
T109	805609	0	0	0
T110	499901	0	0	0
T111	334537	0	0	0
T112	2489	0	0	0
T113	652240	0	0	0
T114	521904	0	0	0
T115	9483	0	0	0
T116	184460	0	0	0
T117	335566	0	0	0

g_testassertion.FpvSecCmMsgFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T4	474987	20	0	0
T5	0	10	0	0
T6	0	20	0	0
T99	0	20	0	0
T100	0	20	0	0
T109	805609	0	0	0
T110	499901	0	0	0
T111	334537	0	0	0
T112	2489	0	0	0
T113	652240	0	0	0
T114	521904	0	0	0
T115	9483	0	0	0
T116	184460	0	0	0
T117	335566	0	0	0

g_testassertion.FpvSecCmMsgFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T4	474987	20	0	0
T5	0	10	0	0
T6	0	20	0	0
T99	0	20	0	0
T100	0	20	0	0
T109	805609	0	0	0
T110	499901	0	0	0
T111	334537	0	0	0
T112	2489	0	0	0
T113	652240	0	0	0
T114	521904	0	0	0
T115	9483	0	0	0
T116	184460	0	0	0
T117	335566	0	0	0

g_testassertion.FpvSecCmPackerCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T4	474987	20	0	0
T5	0	10	0	0
T6	0	20	0	0
T99	0	20	0	0
T100	0	20	0	0
T109	805609	0	0	0
T110	499901	0	0	0
T111	334537	0	0	0
T112	2489	0	0	0
T113	652240	0	0	0
T114	521904	0	0	0
T115	9483	0	0	0
T116	184460	0	0	0
T117	335566	0	0	0

g_testassertion.FpvSecCmSeedIdxCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T4	474987	20	0	0
T5	0	10	0	0
T6	0	20	0	0
T99	0	20	0	0
T100	0	20	0	0
T109	805609	0	0	0
T110	499901	0	0	0
T111	334537	0	0	0
T112	2489	0	0	0
T113	652240	0	0	0
T114	521904	0	0	0
T115	9483	0	0	0
T116	184460	0	0	0
T117	335566	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2280	2193	0	0
T2	91200	91132	0	0
T3	541845	541839	0	0
T7	525101	525092	0	0
T8	24341	24267	0	0
T30	459864	459813	0	0
T31	131959	131958	0	0
T32	196932	196874	0	0
T33	657340	657332	0	0
T34	739155	739091	0	0