Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	2147483647	345972	0	0
RunThenComplete_M	2147483647	3110419	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345972	0	0
T1	221058	388	0	0
T2	1643	0	0	0
T3	204359	140	0	0
T7	17192	9	0	0
T8	0	310	0	0
T28	716567	160	0	0
T29	433507	146	0	0
T30	18115	9	0	0
T31	40615	9	0	0
T32	307406	97	0	0
T33	0	310	0	0
T34	111861	0	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3110419	0	0
T1	221058	5799	0	0
T2	1643	0	0	0
T3	204359	5464	0	0
T7	17192	31	0	0
T8	0	5462	0	0
T28	716567	5904	0	0
T29	433507	766	0	0
T30	18115	31	0	0
T31	40615	31	0	0
T32	307406	522	0	0
T33	0	5462	0	0
T34	111861	0	0	0