Unified Coverage Report :: Module :: kmac

Module : kmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.56	98.77	96.05	100.00	100.00	96.55	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	98.56	98.77	96.05	100.00	100.00	96.55	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.56	98.77	96.05	100.00	100.00	96.55	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.82	98.38	93.14	99.93	94.55	96.04	98.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
gen_entropy.u_entropy	99.29	100.00	95.74	100.00	100.00	100.00	100.00
gen_entropy.u_prim_sync_reqack_data	95.83	100.00	83.33			100.00	100.00
intr_fifo_empty	93.75	100.00	75.00			100.00	100.00
intr_kmac_done	93.75	100.00	75.00			100.00	100.00
intr_kmac_err	93.75	100.00	75.00			100.00	100.00
kmac_csr_assert	100.00						100.00
sha3pad_assert_cov_if	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_app_intf	97.42	97.45	90.82		100.00	98.82	100.00
u_errchk	94.60	95.06	94.59		90.00	93.33	100.00
u_kmac_core	95.80	98.88	92.86	100.00	100.00	91.38	91.67
u_msgfifo	97.32	100.00	95.16	94.52	100.00	94.23	100.00
u_prim_lc_sync	100.00	100.00				100.00	100.00
u_reg	98.99	99.41	96.63	100.00		98.94	100.00
u_sha3	96.50	98.83	95.67	100.00	88.10	96.40	100.00
u_sha3_done_sender	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00
u_staterd	89.71	89.72	80.83			88.30	100.00
u_tlul_adapter_msgfifo	79.67	86.78	73.83			76.83	81.25

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : kmac

	Line No.	Total	Covered	Percent
TOTAL		163	161	98.77
ALWAYS	343	0	0
ALWAYS	343	2	2	100.00
ALWAYS	349	1	0	0.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
ALWAYS	426	9	9	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
ALWAYS	485	6	6	100.00
ALWAYS	498	6	6	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	542	1	1	100.00
CONT_ASSIGN	544	1	1	100.00
CONT_ASSIGN	545	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
ALWAYS	560	5	5	100.00
CONT_ASSIGN	570	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	589	1	1	100.00
ALWAYS	609	3	3	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	632	1	1	100.00
CONT_ASSIGN	637	1	1	100.00
ALWAYS	640	7	7	100.00
CONT_ASSIGN	676	1	1	100.00
CONT_ASSIGN	681	1	1	100.00
CONT_ASSIGN	688	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
ALWAYS	718	3	3	100.00
ALWAYS	722	28	28	100.00
ALWAYS	860	3	3	100.00
CONT_ASSIGN	868	1	1	100.00
CONT_ASSIGN	868	1	1	100.00
CONT_ASSIGN	939	1	1	100.00
CONT_ASSIGN	941	1	1	100.00
CONT_ASSIGN	971	1	1	100.00
CONT_ASSIGN	976	1	1	100.00
CONT_ASSIGN	977	1	1	100.00
CONT_ASSIGN	979	1	1	100.00
CONT_ASSIGN	982	0	0
ALWAYS	1100	0	0
ALWAYS	1100	2	2	100.00
CONT_ASSIGN	1186	1	1	100.00
CONT_ASSIGN	1326	1	1	100.00
CONT_ASSIGN	1340	1	1	100.00
CONT_ASSIGN	1347	1	1	100.00
CONT_ASSIGN	1352	1	1	100.00
ALWAYS	1358	6	5	83.33
CONT_ASSIGN	1367	1	1	100.00
CONT_ASSIGN	1369	1	1	100.00
ALWAYS	1381	4	4	100.00
CONT_ASSIGN	1387	1	1	100.00
ALWAYS	1410	4	4	100.00
ALWAYS	1420	3	3	100.00
CONT_ASSIGN	1431	1	1	100.00
CONT_ASSIGN	1435	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
343	1	1
344	1	1
349	0	1
418	1	1
419	1	1
423	1	1
426	1	1
427	1	1
428	1	1
429	1	1
431	1	1
433	1	1
437	1	1
441	1	1
445	1	1
461	1	1
462	1	1
463	1	1
466	1	1
470	1	1
471	1	1
475	1	1
478	1	1
485	1	1
486	1	1
487	1	1
488	1	1
489	1	1
490	1	1
			MISSING_ELSE
			MISSING_ELSE
498	1	1
499	1	1
500	1	1
501	1	1
502	1	1
503	1	1
			MISSING_ELSE
			MISSING_ELSE
515	1	1
522	1	1
525	1	1
526	1	1
527	1	1
530	5	5
531	5	5
534	1	1
536	1	1
538	1	1
542	1	1
544	1	1
545	1	1
548	1	1
549	1	1
552	1	1
560	1	1
561	1	1
562	1	1
563	1	1
565	1	1
570	1	1
577	1	1
578	1	1
579	1	1
589	1	1
609	2	2
610	1	1
613	1	1
632	1	1
637	1	1
640	1	1
642	1	1
647	1	1
651	1	1
655	1	1
659	1	1
663	1	1
676	1	1
681	1	1
688	1	1
698	1	1
718	3	3
722	1	1
724	1	1
725	1	1
727	1	1
729	1	1
731	1	1
732	1	1
735	1	1
738	1	1
744	1	1
745	1	1
747	1	1
752	1	1
753	1	1
754	1	1
756	1	1
762	1	1
767	1	1
768	1	1
770	1	1
772	1	1
778	1	1
779	1	1
781	1	1
787	1	1
788	1	1
800	1	1
801	1	1
			MISSING_ELSE
860	1	1
861	1	1
863	1	1
868	2	2
939	1	1
941	1	1
971	1	1
976	1	1
977	1	1
979	1	1
982		unreachable
1100	1	1
1101	1	1
1186	1	1
1326	1	1
1340	1	1
1347	1	1
1352	1	1
1358	1	1
1359	1	1
1360	1	1
1361	0	1
1362	1	1
1363	1	1
			MISSING_ELSE
1367	1	1
1369	1	1
1381	1	1
1382	1	1
1383	1	1
1384	1	1
			MISSING_ELSE
1387	1	1
1410	1	1
1411	1	1
1412	1	1
1414	1	1
			MISSING_ELSE
1420	1	1
1421	1	1
1424	1	1
1431	1	1
1435	1	1
1437	6	6

---

Cond Coverage for Module : kmac

	Total	Covered	Percent
Conditions	76	73	96.05
Logical	76	73	96.05
Non-Logical	0	0
Event	0	0

 LINE       423
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       461
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       462
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       463
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       475
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       527
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T73,T74

 LINE       538
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T73,T74

 LINE       542
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T50,T69
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       549
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T3,T7
1	1	1	Covered	T1,T3,T7

 LINE       562
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       562
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       562
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T7
1	-	Covered	T1,T2,T3

 LINE       570
 EXPRESSION (reg2hw.cfg_shadowed.err_processed.q & reg2hw.cfg_shadowed.err_processed.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T34,T69,T51
1	1	Covered	T34,T69,T51

 LINE       613
 EXPRESSION (((~msgfifo_empty_q)) & msgfifo_empty)
             ----------1---------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       632
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T58,T59,T60
0	0	1	0	Covered	T69,T75,T84
0	1	0	0	Covered	T34,T51,T58
1	0	0	0	Covered	T1,T37,T38

 LINE       676
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T4,T5,T6
0	0	1	0	Covered	T4,T5,T6
0	1	0	0	Covered	T4,T5,T6
1	0	0	0	Covered	T4,T5,T6

 LINE       688
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T4,T5,T6
0	0	0	0	1	0	Covered	T4,T5,T6
0	0	0	1	0	0	Covered	T4,T5,T6
0	0	1	0	0	0	Covered	T4,T5,T6
0	1	0	0	0	0	Covered	T4,T5,T6
1	0	0	0	0	0	Covered	T4,T5,T6

 LINE       729
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       731
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T28
1	Covered	T1,T3,T7

 LINE       745
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T32,T50
1	Covered	T1,T3,T7

 LINE       971
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Not Covered
1	1	Covered	T1,T3,T7

 LINE       1101
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       1340
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T103,T104
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T103,T104

 LINE       1340
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T103,T104
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T103,T104

 LINE       1369
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T4,T5,T6
0	0	1	0	0	Covered	T10,T11,T12
0	1	0	0	0	Covered	T4,T5,T6
1	0	0	0	0	Not Covered

---

Toggle Coverage for Module : kmac

	Total	Covered	Percent
Totals	71	71	100.00
Total Bits	6534	6534	100.00
Total Bits 0->1	3267	3267	100.00
Total Bits 1->0	3267	3267	100.00

Ports	71	71	100.00
Port Bits	6534	6534	100.00
Port Bits 0->1	3267	3267	100.00
Port Bits 1->0	3267	3267	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T37,T10	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T7	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T31	Yes	T1,T3,T31	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T7	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T43,T44,T68	Yes	T43,T44,T68	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T7	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T3,T7	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T103,T104	Yes	T2,T103,T104	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T103,T104	Yes	T2,T103,T104	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T103,T104	Yes	T2,T103,T104	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T103,T104	Yes	T2,T103,T104	OUTPUT
keymgr_key_i.key[1:0][255:0]	Yes	Yes	T1,T3,T28	Yes	T1,T3,T28	INPUT
keymgr_key_i.valid	Yes	Yes	T1,T3,T28	Yes	T1,T3,T28	INPUT
app_i[0].last	Yes	Yes	T1,T32,T50	Yes	T1,T32,T50	INPUT
app_i[0].strb[7:0]	Yes	Yes	T1,T57,T73	Yes	T1,T57,T73	INPUT
app_i[0].data[63:0]	Yes	Yes	T1,T34,T32	Yes	T1,T34,T32	INPUT
app_i[0].valid	Yes	Yes	T1,T34,T32	Yes	T1,T34,T32	INPUT
app_i[1].last	Yes	Yes	T1,T32,T50	Yes	T1,T32,T50	INPUT
app_i[1].strb[7:0]	Yes	Yes	T1,T57,T73	Yes	T1,T57,T73	INPUT
app_i[1].data[63:0]	Yes	Yes	T1,T32,T50	Yes	T1,T32,T50	INPUT
app_i[1].valid	Yes	Yes	T1,T32,T50	Yes	T1,T32,T50	INPUT
app_i[2].last	Yes	Yes	T1,T32,T50	Yes	T1,T32,T50	INPUT
app_i[2].strb[7:0]	Yes	Yes	T1,T57,T73	Yes	T1,T57,T73	INPUT
app_i[2].data[63:0]	Yes	Yes	T1,T32,T50	Yes	T1,T32,T50	INPUT
app_i[2].valid	Yes	Yes	T1,T32,T50	Yes	T1,T32,T50	INPUT
app_o[0].error	Yes	Yes	T1,T50,T51	Yes	T1,T50,T51	OUTPUT
app_o[0].digest_share1[383:0]	Yes	Yes	T1,T32,T49	Yes	T1,T32,T49	OUTPUT
app_o[0].digest_share0[383:0]	Yes	Yes	T1,T32,T49	Yes	T1,T32,T49	OUTPUT
app_o[0].done	Yes	Yes	T1,T32,T50	Yes	T1,T32,T50	OUTPUT
app_o[0].ready	Yes	Yes	T1,T34,T32	Yes	T1,T34,T32	OUTPUT
app_o[1].error	Yes	Yes	T1,T37,T38	Yes	T1,T37,T38	OUTPUT
app_o[1].digest_share1[383:0]	Yes	Yes	T1,T32,T50	Yes	T1,T32,T50	OUTPUT
app_o[1].digest_share0[383:0]	Yes	Yes	T1,T32,T50	Yes	T1,T32,T50	OUTPUT
app_o[1].done	Yes	Yes	T1,T32,T50	Yes	T1,T32,T50	OUTPUT
app_o[1].ready	Yes	Yes	T1,T32,T50	Yes	T1,T32,T50	OUTPUT
app_o[2].error	Yes	Yes	T1,T37,T38	Yes	T1,T37,T38	OUTPUT
app_o[2].digest_share1[383:0]	Yes	Yes	T1,T32,T50	Yes	T1,T32,T50	OUTPUT
app_o[2].digest_share0[383:0]	Yes	Yes	T1,T32,T50	Yes	T1,T32,T50	OUTPUT
app_o[2].done	Yes	Yes	T1,T32,T50	Yes	T1,T32,T50	OUTPUT
app_o[2].ready	Yes	Yes	T1,T32,T50	Yes	T1,T32,T50	OUTPUT
entropy_o.edn_req	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
entropy_i.edn_bus[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T28	INPUT
entropy_i.edn_fips	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
entropy_i.edn_ack	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
intr_kmac_done_o	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
intr_fifo_empty_o	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
intr_kmac_err_o	Yes	Yes	T1,T34,T69	Yes	T1,T34,T69	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : kmac

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	770	Covered	T1,T3,T7
KmacIdle	738	Covered	T1,T2,T3
KmacKeyBlock	745	Covered	T1,T3,T7
KmacMsgFeed	735	Covered	T1,T3,T7
KmacPrefix	732	Covered	T1,T3,T7
KmacTerminalError	787	Covered	T10,T11,T12

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	779	Covered	T1,T3,T7
KmacDigest->KmacTerminalError	801	Covered	T12,T36
KmacIdle->KmacMsgFeed	735	Covered	T1,T3,T28
KmacIdle->KmacPrefix	732	Covered	T1,T3,T7
KmacIdle->KmacTerminalError	801	Covered	T4,T35,T5
KmacKeyBlock->KmacMsgFeed	754	Covered	T1,T3,T7
KmacKeyBlock->KmacTerminalError	801	Covered	T23,T105,T62
KmacMsgFeed->KmacDigest	770	Covered	T1,T3,T7
KmacMsgFeed->KmacIdle	767	Covered	T1,T32,T50
KmacMsgFeed->KmacTerminalError	801	Covered	T13,T14,T64
KmacPrefix->KmacKeyBlock	745	Covered	T1,T3,T7
KmacPrefix->KmacMsgFeed	745	Covered	T1,T32,T50
KmacPrefix->KmacTerminalError	801	Covered	T10,T11,T22

---

Branch Coverage for Module : kmac

	Line No.	Total	Covered	Percent
Branches		58	56	96.55
TERNARY	423	2	2	100.00
CASE	431	6	5	83.33
IF	485	3	3	100.00
IF	560	3	3	100.00
IF	609	2	2	100.00
CASE	642	6	6	100.00
IF	718	2	2	100.00
CASE	727	15	15	100.00
IF	800	2	2	100.00
TERNARY	1101	2	2	100.00
IF	1358	4	3	75.00
IF	1381	3	3	100.00
IF	1410	3	3	100.00
IF	1420	2	2	100.00
IF	498	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	423	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	431	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Covered	T1,T3,T7
CmdProcess	Covered	T1,T3,T7
CmdManualRun	Covered	T1,T3,T28
CmdDone	Covered	T1,T3,T7
CmdNone	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	485	if ((!rst_ni))
-2-:	487	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	560	if ((!rst_ni))
-2-:	562	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	609	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	642	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Covered	T34,T51,T58
errchecker_err.valid	Covered	T58,T59,T60
sha3_err.valid	Covered	T1,T37,T38
entropy_err.valid	Covered	T69,T75,T84
msgfifo_err.valid	Covered	T4,T5,T6
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	718	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	727	case (kmac_st)
-2-:	729	if ((kmac_cmd == CmdStart))
-3-:	731	if ((CShake == app_sha3_mode))
-4-:	744	if (sha3_block_processed)
-5-:	745	(app_kmac_en) ? 
-6-:	753	if (sha3_block_processed)
-7-:	762	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	768	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	778	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T1,T3,T7
KmacIdle	1	0	-	-	-	-	-	-	Covered	T1,T3,T28
KmacIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T1,T3,T7
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T1,T32,T50
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T1,T3,T7
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T1,T3,T7
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T1,T3,T7
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T1,T32,T50
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T1,T3,T7
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T1,T3,T7
KmacDigest	-	-	-	-	-	-	-	1	Covered	T1,T3,T7
KmacDigest	-	-	-	-	-	-	-	0	Covered	T1,T3,T7
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	800	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1101	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1358	if ((!rst_ni))
-2-:	1360	if (alert_recov_operation)
-3-:	1362	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T34,T69,T51
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1381	if ((!rst_ni))
-2-:	1383	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1410	if ((!rst_ni))
-2-:	1412	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1420	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	498	if ((!rst_ni))
-2-:	500	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T3,T7

---

Assert Coverage for Module : kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	2147483647	2147483647	0	0
CmdSparse_M	2147483647	1279323	0	0
EnMaskingKnown_A	2147483647	2147483647	0	0
EntropyReadyLatched_A	2147483647	336923	0	0
EntrySizeRegSameToEntrySizePkg_A	1031	1031	0	0
ErrProcessedLatched_A	2147483647	799	0	0
FifoEmpty_A	2147483647	2147483647	0	0
FpvSecCmErrorCheckFsmCheck_A	2147483647	70	0	0
FpvSecCmKeccackFsmCheck_A	2147483647	70	0	0
FpvSecCmKeyIndexCountCheck_A	2147483647	70	0	0
FpvSecCmKmacAppFsmCheck_A	2147483647	70	0	0
FpvSecCmKmacCoreFsmCheck_A	2147483647	70	0	0
FpvSecCmKmacFsmCheck_A	2147483647	70	0	0
FpvSecCmRegWeOnehotCheck_A	2147483647	70	0	0
FpvSecCmRoundCountCheck_A	2147483647	70	0	0
FpvSecCmSHA3FsmCheck_A	2147483647	70	0	0
FpvSecCmSHA3padFsmCheck_A	2147483647	70	0	0
FpvSecCmSentMsgCountCheck_A	2147483647	70	0	0
KmacCmd_A	2147483647	2147483647	0	0
KmacDone_A	2147483647	2147483647	0	0
KmacErr_A	2147483647	2147483647	0	0
KmacStKnown_A	2147483647	2147483647	0	0
NumAlerts2_A	1031	1031	0	0
NumEntriesRegSameToNumEntriesPkg_A	1031	1031	0	0
PrefixRegSameToPrefixPkg_A	1031	1031	0	0
SecretKeyDivideBy32_A	1031	1031	0	0
Sha3AbsorbedPulse_A	2147483647	345954	0	0
TlOAReadyKnown_A	2147483647	2147483647	0	0
TlODValidKnown_A	2147483647	2147483647	0	0
g_testassertion.FpvSecCmEntropyFsmCheck_A	2147483647	70	0	0
g_testassertion.FpvSecCmHashCountCheck_A	2147483647	70	0	0
g_testassertion.FpvSecCmMsgFifoRptrCheck_A	2147483647	70	0	0
g_testassertion.FpvSecCmMsgFifoWptrCheck_A	2147483647	70	0	0
g_testassertion.FpvSecCmPackerCountCheck_A	2147483647	70	0	0
g_testassertion.FpvSecCmSeedIdxCountCheck_A	2147483647	70	0	0
u_state_regs_A	2147483647	2147483647	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	221058	220983	0	0
T2	1643	1583	0	0
T3	204359	204352	0	0
T7	17192	17101	0	0
T28	716567	716559	0	0
T29	433507	433422	0	0
T30	18115	18026	0	0
T31	40615	40552	0	0
T32	307406	307340	0	0
T34	111861	111793	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1279323	0	0
T1	221058	2182	0	0
T2	1643	0	0	0
T3	204359	1008	0	0
T7	17192	30	0	0
T28	716567	1135	0	0
T29	433507	1035	0	0
T30	18115	28	0	0
T31	40615	29	0	0
T32	307406	528	0	0
T33	0	986	0	0
T34	111861	4	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	221058	220983	0	0
T2	1643	1583	0	0
T3	204359	204352	0	0
T7	17192	17101	0	0
T28	716567	716559	0	0
T29	433507	433422	0	0
T30	18115	18026	0	0
T31	40615	40552	0	0
T32	307406	307340	0	0
T34	111861	111793	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	336923	0	0
T1	221058	386	0	0
T2	1643	0	0	0
T3	204359	140	0	0
T7	17192	9	0	0
T28	716567	159	0	0
T29	433507	146	0	0
T30	18115	9	0	0
T31	40615	9	0	0
T32	307406	97	0	0
T33	0	303	0	0
T34	111861	17	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1031	1031	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	799	0	0
T8	146198	0	0	0
T31	40615	0	0	0
T32	307406	0	0	0
T33	707792	0	0	0
T34	111861	17	0	0
T46	629128	0	0	0
T47	763411	0	0	0
T50	514685	0	0	0
T51	0	13	0	0
T52	0	20	0	0
T56	0	14	0	0
T69	0	14	0	0
T75	0	12	0	0
T84	0	8	0	0
T87	610233	0	0	0
T103	1416	0	0	0
T106	0	16	0	0
T107	0	1	0	0
T108	0	18	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	221058	220983	0	0
T2	1643	1583	0	0
T3	204359	204352	0	0
T7	17192	17101	0	0
T28	716567	716559	0	0
T29	433507	433422	0	0
T30	18115	18026	0	0
T31	40615	40552	0	0
T32	307406	307340	0	0
T34	111861	111793	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70	0	0
T4	755807	20	0	0
T5	0	10	0	0
T6	0	10	0	0
T78	3785	0	0	0
T109	0	20	0	0
T110	0	10	0	0
T111	145696	0	0	0
T112	127308	0	0	0
T113	73611	0	0	0
T114	270039	0	0	0
T115	938820	0	0	0
T116	713862	0	0	0
T117	648045	0	0	0
T118	258683	0	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70	0	0
T4	755807	20	0	0
T5	0	10	0	0
T6	0	10	0	0
T78	3785	0	0	0
T109	0	20	0	0
T110	0	10	0	0
T111	145696	0	0	0
T112	127308	0	0	0
T113	73611	0	0	0
T114	270039	0	0	0
T115	938820	0	0	0
T116	713862	0	0	0
T117	648045	0	0	0
T118	258683	0	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70	0	0
T4	755807	20	0	0
T5	0	10	0	0
T6	0	10	0	0
T78	3785	0	0	0
T109	0	20	0	0
T110	0	10	0	0
T111	145696	0	0	0
T112	127308	0	0	0
T113	73611	0	0	0
T114	270039	0	0	0
T115	938820	0	0	0
T116	713862	0	0	0
T117	648045	0	0	0
T118	258683	0	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70	0	0
T4	755807	20	0	0
T5	0	10	0	0
T6	0	10	0	0
T78	3785	0	0	0
T109	0	20	0	0
T110	0	10	0	0
T111	145696	0	0	0
T112	127308	0	0	0
T113	73611	0	0	0
T114	270039	0	0	0
T115	938820	0	0	0
T116	713862	0	0	0
T117	648045	0	0	0
T118	258683	0	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70	0	0
T4	755807	20	0	0
T5	0	10	0	0
T6	0	10	0	0
T78	3785	0	0	0
T109	0	20	0	0
T110	0	10	0	0
T111	145696	0	0	0
T112	127308	0	0	0
T113	73611	0	0	0
T114	270039	0	0	0
T115	938820	0	0	0
T116	713862	0	0	0
T117	648045	0	0	0
T118	258683	0	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70	0	0
T4	755807	20	0	0
T5	0	10	0	0
T6	0	10	0	0
T78	3785	0	0	0
T109	0	20	0	0
T110	0	10	0	0
T111	145696	0	0	0
T112	127308	0	0	0
T113	73611	0	0	0
T114	270039	0	0	0
T115	938820	0	0	0
T116	713862	0	0	0
T117	648045	0	0	0
T118	258683	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70	0	0
T4	755807	20	0	0
T5	0	10	0	0
T6	0	10	0	0
T78	3785	0	0	0
T109	0	20	0	0
T110	0	10	0	0
T111	145696	0	0	0
T112	127308	0	0	0
T113	73611	0	0	0
T114	270039	0	0	0
T115	938820	0	0	0
T116	713862	0	0	0
T117	648045	0	0	0
T118	258683	0	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70	0	0
T4	755807	20	0	0
T5	0	10	0	0
T6	0	10	0	0
T78	3785	0	0	0
T109	0	20	0	0
T110	0	10	0	0
T111	145696	0	0	0
T112	127308	0	0	0
T113	73611	0	0	0
T114	270039	0	0	0
T115	938820	0	0	0
T116	713862	0	0	0
T117	648045	0	0	0
T118	258683	0	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70	0	0
T4	755807	20	0	0
T5	0	10	0	0
T6	0	10	0	0
T78	3785	0	0	0
T109	0	20	0	0
T110	0	10	0	0
T111	145696	0	0	0
T112	127308	0	0	0
T113	73611	0	0	0
T114	270039	0	0	0
T115	938820	0	0	0
T116	713862	0	0	0
T117	648045	0	0	0
T118	258683	0	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70	0	0
T4	755807	20	0	0
T5	0	10	0	0
T6	0	10	0	0
T78	3785	0	0	0
T109	0	20	0	0
T110	0	10	0	0
T111	145696	0	0	0
T112	127308	0	0	0
T113	73611	0	0	0
T114	270039	0	0	0
T115	938820	0	0	0
T116	713862	0	0	0
T117	648045	0	0	0
T118	258683	0	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70	0	0
T4	755807	20	0	0
T5	0	10	0	0
T6	0	10	0	0
T78	3785	0	0	0
T109	0	20	0	0
T110	0	10	0	0
T111	145696	0	0	0
T112	127308	0	0	0
T113	73611	0	0	0
T114	270039	0	0	0
T115	938820	0	0	0
T116	713862	0	0	0
T117	648045	0	0	0
T118	258683	0	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	221058	220983	0	0
T2	1643	1583	0	0
T3	204359	204352	0	0
T7	17192	17101	0	0
T28	716567	716559	0	0
T29	433507	433422	0	0
T30	18115	18026	0	0
T31	40615	40552	0	0
T32	307406	307340	0	0
T34	111861	111793	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	221058	220983	0	0
T2	1643	1583	0	0
T3	204359	204352	0	0
T7	17192	17101	0	0
T28	716567	716559	0	0
T29	433507	433422	0	0
T30	18115	18026	0	0
T31	40615	40552	0	0
T32	307406	307340	0	0
T34	111861	111793	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	221058	220983	0	0
T2	1643	1583	0	0
T3	204359	204352	0	0
T7	17192	17101	0	0
T28	716567	716559	0	0
T29	433507	433422	0	0
T30	18115	18026	0	0
T31	40615	40552	0	0
T32	307406	307340	0	0
T34	111861	111793	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	221058	220983	0	0
T2	1643	1583	0	0
T3	204359	204352	0	0
T7	17192	17101	0	0
T28	716567	716559	0	0
T29	433507	433422	0	0
T30	18115	18026	0	0
T31	40615	40552	0	0
T32	307406	307340	0	0
T34	111861	111793	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1031	1031	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1031	1031	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1031	1031	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1031	1031	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345954	0	0
T1	221058	388	0	0
T2	1643	0	0	0
T3	204359	140	0	0
T7	17192	9	0	0
T8	0	310	0	0
T28	716567	160	0	0
T29	433507	146	0	0
T30	18115	9	0	0
T31	40615	9	0	0
T32	307406	97	0	0
T33	0	310	0	0
T34	111861	0	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	221058	220983	0	0
T2	1643	1583	0	0
T3	204359	204352	0	0
T7	17192	17101	0	0
T28	716567	716559	0	0
T29	433507	433422	0	0
T30	18115	18026	0	0
T31	40615	40552	0	0
T32	307406	307340	0	0
T34	111861	111793	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	221058	220983	0	0
T2	1643	1583	0	0
T3	204359	204352	0	0
T7	17192	17101	0	0
T28	716567	716559	0	0
T29	433507	433422	0	0
T30	18115	18026	0	0
T31	40615	40552	0	0
T32	307406	307340	0	0
T34	111861	111793	0	0

g_testassertion.FpvSecCmEntropyFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70	0	0
T4	755807	20	0	0
T5	0	10	0	0
T6	0	10	0	0
T78	3785	0	0	0
T109	0	20	0	0
T110	0	10	0	0
T111	145696	0	0	0
T112	127308	0	0	0
T113	73611	0	0	0
T114	270039	0	0	0
T115	938820	0	0	0
T116	713862	0	0	0
T117	648045	0	0	0
T118	258683	0	0	0

g_testassertion.FpvSecCmHashCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70	0	0
T4	755807	20	0	0
T5	0	10	0	0
T6	0	10	0	0
T78	3785	0	0	0
T109	0	20	0	0
T110	0	10	0	0
T111	145696	0	0	0
T112	127308	0	0	0
T113	73611	0	0	0
T114	270039	0	0	0
T115	938820	0	0	0
T116	713862	0	0	0
T117	648045	0	0	0
T118	258683	0	0	0

g_testassertion.FpvSecCmMsgFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70	0	0
T4	755807	20	0	0
T5	0	10	0	0
T6	0	10	0	0
T78	3785	0	0	0
T109	0	20	0	0
T110	0	10	0	0
T111	145696	0	0	0
T112	127308	0	0	0
T113	73611	0	0	0
T114	270039	0	0	0
T115	938820	0	0	0
T116	713862	0	0	0
T117	648045	0	0	0
T118	258683	0	0	0

g_testassertion.FpvSecCmMsgFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70	0	0
T4	755807	20	0	0
T5	0	10	0	0
T6	0	10	0	0
T78	3785	0	0	0
T109	0	20	0	0
T110	0	10	0	0
T111	145696	0	0	0
T112	127308	0	0	0
T113	73611	0	0	0
T114	270039	0	0	0
T115	938820	0	0	0
T116	713862	0	0	0
T117	648045	0	0	0
T118	258683	0	0	0

g_testassertion.FpvSecCmPackerCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70	0	0
T4	755807	20	0	0
T5	0	10	0	0
T6	0	10	0	0
T78	3785	0	0	0
T109	0	20	0	0
T110	0	10	0	0
T111	145696	0	0	0
T112	127308	0	0	0
T113	73611	0	0	0
T114	270039	0	0	0
T115	938820	0	0	0
T116	713862	0	0	0
T117	648045	0	0	0
T118	258683	0	0	0

g_testassertion.FpvSecCmSeedIdxCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70	0	0
T4	755807	20	0	0
T5	0	10	0	0
T6	0	10	0	0
T78	3785	0	0	0
T109	0	20	0	0
T110	0	10	0	0
T111	145696	0	0	0
T112	127308	0	0	0
T113	73611	0	0	0
T114	270039	0	0	0
T115	938820	0	0	0
T116	713862	0	0	0
T117	648045	0	0	0
T118	258683	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	221058	220983	0	0
T2	1643	1583	0	0
T3	204359	204352	0	0
T7	17192	17101	0	0
T28	716567	716559	0	0
T29	433507	433422	0	0
T30	18115	18026	0	0
T31	40615	40552	0	0
T32	307406	307340	0	0
T34	111861	111793	0	0