Unified Coverage Report :: Module :: kmac_core

Module : kmac_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	98.68	92.86		100.00	91.07	88.89

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_kmac_core	94.30	98.68	92.86		100.00	91.07	88.89

---

Module Instance : tb.dut.u_kmac_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	98.68	92.86		100.00	91.07	88.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.80	98.88	92.86	100.00	100.00	91.38	91.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_key_slicer[0].u_key_slicer	100.00	100.00					100.00
gen_key_slicer[1].u_key_slicer	100.00	100.00					100.00
u_key_index_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : kmac_core

	Line No.	Total	Covered	Percent
TOTAL		76	75	98.68
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	3	3	100.00
ALWAYS	164	30	30	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
ALWAYS	266	6	5	83.33
CONT_ASSIGN	285	1	1	100.00
ALWAYS	305	6	6	100.00
ALWAYS	336	6	6	100.00
ALWAYS	336	6	6	100.00
CONT_ASSIGN	370	1	1	100.00
CONT_ASSIGN	373	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
ALWAYS	418	6	6	100.00
CONT_ASSIGN	429	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
151	1	1
159	3	3
164	1	1
166	1	1
167	1	1
169	1	1
171	1	1
172	1	1
174	1	1
176	1	1
178	1	1
179	1	1
181	1	1
188	1	1
189	1	1
191	1	1
192	1	1
194	1	1
195	1	1
197	1	1
199	1	1
205	1	1
206	1	1
208	1	1
210	1	1
215	1	1
216	1	1
218	1	1
224	1	1
225	1	1
238	1	1
239	1	1
			MISSING_ELSE
249	1	1
250	1	1
251	1	1
252	1	1
256	1	1
258	1	1
263	1	1
266	1	1
267	1	1
268	1	1
269	0	1
270	1	1
272	1	1
			MISSING_ELSE
285	1	1
305	1	1
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
336	1	1
339	1	1
343	1	1
347	1	1
351	1	1
356	1	1
336	1	1
339	1	1
343	1	1
347	1	1
351	1	1
356	1	1
370	1	1
373	1	1
392	1	1
418	1	1
419	1	1
420	1	1
421	1	1
422	1	1
423	1	1
429	1	1

---

Cond Coverage for Module : kmac_core

	Total	Covered	Percent
Conditions	28	26	92.86
Logical	28	26	92.86
Non-Logical	0	0
Event	0	0

 LINE       178
 EXPRESSION (kmac_en_i && start_i)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T28
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       205
 EXPRESSION (process_i || process_latched)
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T7
0	1	Not Covered
1	0	Covered	T1,T3,T7

 LINE       249
 EXPRESSION (en_kmac_datapath ? kmac_valid : fifo_valid_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       250
 EXPRESSION (en_kmac_datapath ? kmac_data : fifo_data_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       251
 EXPRESSION (en_kmac_datapath ? kmac_strb : fifo_strb_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       252
 EXPRESSION (en_kmac_datapath ? 1'b0 : msg_ready_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       256
 EXPRESSION (en_key_write ? '1 : '0)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       258
 EXPRESSION (en_key_write ? key_sliced : ('{(*adjust*)default:'0}))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       263
 EXPRESSION (kmac_en_i ? kmac_process : process_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       268
 EXPRESSION (process_i && ((!process_o)))
             ----1----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Not Covered

 LINE       392
 EXPRESSION (kmac_valid & msg_ready_i)
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       429
 EXPRESSION (key_index == block_addr_limit)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

---

FSM Coverage for Module : kmac_core

Summary for FSM :: st

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	8	8	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StKey	179	Covered	T1,T3,T7
StKmacFlush	206	Covered	T1,T3,T7
StKmacIdle	181	Covered	T1,T2,T3
StKmacMsg	192	Covered	T1,T3,T7
StTerminalError	239	Covered	T10,T11,T12

transitions	Line No.	Covered	Tests
StKey->StKmacMsg	192	Covered	T1,T3,T7
StKey->StTerminalError	239	Covered	T11,T22,T16
StKmacFlush->StKmacIdle	216	Covered	T1,T3,T7
StKmacFlush->StTerminalError	239	Covered	T36
StKmacIdle->StKey	179	Covered	T1,T3,T7
StKmacIdle->StTerminalError	239	Covered	T10,T12,T13
StKmacMsg->StKmacFlush	206	Covered	T1,T3,T7
StKmacMsg->StTerminalError	239	Covered	T23,T62,T70

---

Branch Coverage for Module : kmac_core

	Line No.	Total	Covered	Percent
Branches		56	51	91.07
TERNARY	249	2	2	100.00
TERNARY	250	2	2	100.00
TERNARY	251	2	2	100.00
TERNARY	252	2	2	100.00
TERNARY	256	2	2	100.00
TERNARY	258	2	2	100.00
TERNARY	263	2	2	100.00
IF	159	2	2	100.00
CASE	176	10	10	100.00
IF	238	2	2	100.00
IF	266	4	3	75.00
CASE	305	6	5	83.33
CASE	418	6	5	83.33
CASE	336	6	5	83.33
CASE	336	6	5	83.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	249	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	250	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	251	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	252	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	256	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	258	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	263	(kmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	159	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	176	case (st)
-2-:	178	if ((kmac_en_i && start_i))
-3-:	191	if (sent_blocksize)
-4-:	205	if ((process_i || process_latched))
-5-:	215	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StKmacIdle	1	-	-	-	Covered	T1,T3,T7
StKmacIdle	0	-	-	-	Covered	T1,T2,T3
StKey	-	1	-	-	Covered	T1,T3,T7
StKey	-	0	-	-	Covered	T1,T3,T7
StKmacMsg	-	-	1	-	Covered	T1,T3,T7
StKmacMsg	-	-	0	-	Covered	T1,T3,T7
StKmacFlush	-	-	-	1	Covered	T1,T3,T7
StKmacFlush	-	-	-	0	Covered	T1,T3,T7
StTerminalError	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	238	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	266	if ((!rst_ni))
-2-:	268	if ((process_i && (!process_o)))
-3-:	270	if ((process_o || prim_mubi_pkg::mubi4_test_true_strict(done_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T1,T3,T28
Key256	Covered	T1,T3,T7
Key384	Covered	T1,T3,T28
Key512	Covered	T1,T3,T28
default	Not Covered

	LineNo.	Expression
-1-:	418	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T1,T2,T3
L224	Covered	T1,T3,T29
L256	Covered	T1,T2,T3
L384	Covered	T1,T28,T34
L512	Covered	T1,T3,T47
default	Not Covered

	LineNo.	Expression
-1-:	336	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T1,T3,T28
Key256	Covered	T1,T3,T7
Key384	Covered	T1,T3,T28
Key512	Covered	T1,T3,T28
default	Not Covered

	LineNo.	Expression
-1-:	336	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T1,T3,T28
Key256	Covered	T1,T3,T7
Key384	Covered	T1,T3,T28
Key512	Covered	T1,T3,T28
default	Not Covered

---

Assert Coverage for Module : kmac_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	8	88.89
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	8	88.89

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckOnlyInMessageState_A	2147483647	8308270	0	0
KeyDataStable_M	2147483647	1016154	0	0
KeyLengthStable_M	2147483647	281894	0	0
KmacEnStable_M	2147483647	23044	0	0
MaxKeyLenMatchToKey512_A	1031	1031	0	0
ModeStable_M	2147483647	35258	0	0
ProcessLatchedCleared_A	2147483647	0	0	0
StrengthStable_M	2147483647	42031	0	0
u_state_regs_A	2147483647	2147483647	0	0

AckOnlyInMessageState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8308270	0	0
T1	221058	66291	0	0
T2	1643	0	0	0
T3	204359	71695	0	0
T7	17192	109	0	0
T28	716567	84318	0	0
T29	433507	5815	0	0
T30	18115	109	0	0
T31	40615	109	0	0
T32	307406	3355	0	0
T34	111861	0	0	0
T46	0	66524	0	0
T47	0	3995	0	0

KeyDataStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1016154	0	0
T1	221058	7172	0	0
T2	1643	0	0	0
T3	204359	3328	0	0
T7	17192	8	0	0
T28	716567	3936	0	0
T29	433507	3460	0	0
T30	18115	8	0	0
T31	40615	8	0	0
T32	307406	1200	0	0
T34	111861	578	0	0
T50	0	374	0	0

KeyLengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	281894	0	0
T1	221058	279	0	0
T2	1643	0	0	0
T3	204359	109	0	0
T7	17192	1	0	0
T28	716567	127	0	0
T29	433507	3	0	0
T30	18115	1	0	0
T31	40615	1	0	0
T32	307406	125	0	0
T33	0	256	0	0
T34	111861	34	0	0

KmacEnStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	23044	0	0
T1	221058	183	0	0
T2	1643	0	0	0
T3	204359	55	0	0
T7	17192	1	0	0
T28	716567	59	0	0
T29	433507	57	0	0
T30	18115	1	0	0
T31	40615	1	0	0
T32	307406	42	0	0
T34	111861	34	0	0
T50	0	103	0	0

MaxKeyLenMatchToKey512_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1031	1031	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0

ModeStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35258	0	0
T1	221058	245	0	0
T2	1643	0	0	0
T3	204359	55	0	0
T7	17192	1	0	0
T28	716567	59	0	0
T29	433507	59	0	0
T30	18115	1	0	0
T31	40615	1	0	0
T32	307406	91	0	0
T34	111861	42	0	0
T50	0	390	0	0

ProcessLatchedCleared_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

StrengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	42031	0	0
T1	221058	264	0	0
T2	1643	1	0	0
T3	204359	75	0	0
T7	17192	2	0	0
T28	716567	82	0	0
T29	433507	73	0	0
T30	18115	2	0	0
T31	40615	2	0	0
T32	307406	92	0	0
T34	111861	38	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	221058	220983	0	0
T2	1643	1583	0	0
T3	204359	204352	0	0
T7	17192	17101	0	0
T28	716567	716559	0	0
T29	433507	433422	0	0
T30	18115	18026	0	0
T31	40615	40552	0	0
T32	307406	307340	0	0
T34	111861	111793	0	0

Line Coverage for Instance : tb.dut.u_kmac_core

	Line No.	Total	Covered	Percent
TOTAL		76	75	98.68
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	3	3	100.00
ALWAYS	164	30	30	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
ALWAYS	266	6	5	83.33
CONT_ASSIGN	285	1	1	100.00
ALWAYS	305	6	6	100.00
ALWAYS	336	6	6	100.00
ALWAYS	336	6	6	100.00
CONT_ASSIGN	370	1	1	100.00
CONT_ASSIGN	373	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
ALWAYS	418	6	6	100.00
CONT_ASSIGN	429	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
151	1	1
159	3	3
164	1	1
166	1	1
167	1	1
169	1	1
171	1	1
172	1	1
174	1	1
176	1	1
178	1	1
179	1	1
181	1	1
188	1	1
189	1	1
191	1	1
192	1	1
194	1	1
195	1	1
197	1	1
199	1	1
205	1	1
206	1	1
208	1	1
210	1	1
215	1	1
216	1	1
218	1	1
224	1	1
225	1	1
238	1	1
239	1	1
			MISSING_ELSE
249	1	1
250	1	1
251	1	1
252	1	1
256	1	1
258	1	1
263	1	1
266	1	1
267	1	1
268	1	1
269	0	1
270	1	1
272	1	1
			MISSING_ELSE
285	1	1
305	1	1
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
336	1	1
339	1	1
343	1	1
347	1	1
351	1	1
356	1	1
336	1	1
339	1	1
343	1	1
347	1	1
351	1	1
356	1	1
370	1	1
373	1	1
392	1	1
418	1	1
419	1	1
420	1	1
421	1	1
422	1	1
423	1	1
429	1	1

---

Cond Coverage for Instance : tb.dut.u_kmac_core

	Total	Covered	Percent
Conditions	28	26	92.86
Logical	28	26	92.86
Non-Logical	0	0
Event	0	0

 LINE       178
 EXPRESSION (kmac_en_i && start_i)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T28
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       205
 EXPRESSION (process_i || process_latched)
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T7
0	1	Not Covered
1	0	Covered	T1,T3,T7

 LINE       249
 EXPRESSION (en_kmac_datapath ? kmac_valid : fifo_valid_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       250
 EXPRESSION (en_kmac_datapath ? kmac_data : fifo_data_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       251
 EXPRESSION (en_kmac_datapath ? kmac_strb : fifo_strb_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       252
 EXPRESSION (en_kmac_datapath ? 1'b0 : msg_ready_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       256
 EXPRESSION (en_key_write ? '1 : '0)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       258
 EXPRESSION (en_key_write ? key_sliced : ('{(*adjust*)default:'0}))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       263
 EXPRESSION (kmac_en_i ? kmac_process : process_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       268
 EXPRESSION (process_i && ((!process_o)))
             ----1----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Not Covered

 LINE       392
 EXPRESSION (kmac_valid & msg_ready_i)
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       429
 EXPRESSION (key_index == block_addr_limit)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

---

FSM Coverage for Instance : tb.dut.u_kmac_core

Summary for FSM :: st

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StKey	179	Covered	T1,T3,T7
StKmacFlush	206	Covered	T1,T3,T7
StKmacIdle	181	Covered	T1,T2,T3
StKmacMsg	192	Covered	T1,T3,T7
StTerminalError	239	Covered	T10,T11,T12

transitions	Line No.	Covered	Tests	Exclude Annotation
StKey->StKmacMsg	192	Covered	T1,T3,T7
StKey->StTerminalError	239	Covered	T11,T22,T16
StKmacFlush->StKmacIdle	216	Covered	T1,T3,T7
StKmacFlush->StTerminalError	239	Excluded	T36	[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StKmacIdle->StKey	179	Covered	T1,T3,T7
StKmacIdle->StTerminalError	239	Covered	T10,T12,T13
StKmacMsg->StKmacFlush	206	Covered	T1,T3,T7
StKmacMsg->StTerminalError	239	Covered	T23,T62,T70

---

Branch Coverage for Instance : tb.dut.u_kmac_core

	Line No.	Total	Covered	Percent
Branches		56	51	91.07
TERNARY	249	2	2	100.00
TERNARY	250	2	2	100.00
TERNARY	251	2	2	100.00
TERNARY	252	2	2	100.00
TERNARY	256	2	2	100.00
TERNARY	258	2	2	100.00
TERNARY	263	2	2	100.00
IF	159	2	2	100.00
CASE	176	10	10	100.00
IF	238	2	2	100.00
IF	266	4	3	75.00
CASE	305	6	5	83.33
CASE	418	6	5	83.33
CASE	336	6	5	83.33
CASE	336	6	5	83.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	249	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	250	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	251	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	252	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	256	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	258	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	263	(kmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	159	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	176	case (st)
-2-:	178	if ((kmac_en_i && start_i))
-3-:	191	if (sent_blocksize)
-4-:	205	if ((process_i || process_latched))
-5-:	215	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StKmacIdle	1	-	-	-	Covered	T1,T3,T7
StKmacIdle	0	-	-	-	Covered	T1,T2,T3
StKey	-	1	-	-	Covered	T1,T3,T7
StKey	-	0	-	-	Covered	T1,T3,T7
StKmacMsg	-	-	1	-	Covered	T1,T3,T7
StKmacMsg	-	-	0	-	Covered	T1,T3,T7
StKmacFlush	-	-	-	1	Covered	T1,T3,T7
StKmacFlush	-	-	-	0	Covered	T1,T3,T7
StTerminalError	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	238	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	266	if ((!rst_ni))
-2-:	268	if ((process_i && (!process_o)))
-3-:	270	if ((process_o || prim_mubi_pkg::mubi4_test_true_strict(done_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T1,T3,T28
Key256	Covered	T1,T3,T7
Key384	Covered	T1,T3,T28
Key512	Covered	T1,T3,T28
default	Not Covered

	LineNo.	Expression
-1-:	418	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T1,T2,T3
L224	Covered	T1,T3,T29
L256	Covered	T1,T2,T3
L384	Covered	T1,T28,T34
L512	Covered	T1,T3,T47
default	Not Covered

	LineNo.	Expression
-1-:	336	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T1,T3,T28
Key256	Covered	T1,T3,T7
Key384	Covered	T1,T3,T28
Key512	Covered	T1,T3,T28
default	Not Covered

	LineNo.	Expression
-1-:	336	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T1,T3,T28
Key256	Covered	T1,T3,T7
Key384	Covered	T1,T3,T28
Key512	Covered	T1,T3,T28
default	Not Covered

---

Assert Coverage for Instance : tb.dut.u_kmac_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	8	88.89
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	8	88.89

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckOnlyInMessageState_A	2147483647	8308270	0	0
KeyDataStable_M	2147483647	1016154	0	0
KeyLengthStable_M	2147483647	281894	0	0
KmacEnStable_M	2147483647	23044	0	0
MaxKeyLenMatchToKey512_A	1031	1031	0	0
ModeStable_M	2147483647	35258	0	0
ProcessLatchedCleared_A	2147483647	0	0	0
StrengthStable_M	2147483647	42031	0	0
u_state_regs_A	2147483647	2147483647	0	0

AckOnlyInMessageState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8308270	0	0
T1	221058	66291	0	0
T2	1643	0	0	0
T3	204359	71695	0	0
T7	17192	109	0	0
T28	716567	84318	0	0
T29	433507	5815	0	0
T30	18115	109	0	0
T31	40615	109	0	0
T32	307406	3355	0	0
T34	111861	0	0	0
T46	0	66524	0	0
T47	0	3995	0	0

KeyDataStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1016154	0	0
T1	221058	7172	0	0
T2	1643	0	0	0
T3	204359	3328	0	0
T7	17192	8	0	0
T28	716567	3936	0	0
T29	433507	3460	0	0
T30	18115	8	0	0
T31	40615	8	0	0
T32	307406	1200	0	0
T34	111861	578	0	0
T50	0	374	0	0

KeyLengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	281894	0	0
T1	221058	279	0	0
T2	1643	0	0	0
T3	204359	109	0	0
T7	17192	1	0	0
T28	716567	127	0	0
T29	433507	3	0	0
T30	18115	1	0	0
T31	40615	1	0	0
T32	307406	125	0	0
T33	0	256	0	0
T34	111861	34	0	0

KmacEnStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	23044	0	0
T1	221058	183	0	0
T2	1643	0	0	0
T3	204359	55	0	0
T7	17192	1	0	0
T28	716567	59	0	0
T29	433507	57	0	0
T30	18115	1	0	0
T31	40615	1	0	0
T32	307406	42	0	0
T34	111861	34	0	0
T50	0	103	0	0

MaxKeyLenMatchToKey512_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1031	1031	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0

ModeStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35258	0	0
T1	221058	245	0	0
T2	1643	0	0	0
T3	204359	55	0	0
T7	17192	1	0	0
T28	716567	59	0	0
T29	433507	59	0	0
T30	18115	1	0	0
T31	40615	1	0	0
T32	307406	91	0	0
T34	111861	42	0	0
T50	0	390	0	0

ProcessLatchedCleared_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

StrengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	42031	0	0
T1	221058	264	0	0
T2	1643	1	0	0
T3	204359	75	0	0
T7	17192	2	0	0
T28	716567	82	0	0
T29	433507	73	0	0
T30	18115	2	0	0
T31	40615	2	0	0
T32	307406	92	0	0
T34	111861	38	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	221058	220983	0	0
T2	1643	1583	0	0
T3	204359	204352	0	0
T7	17192	17101	0	0
T28	716567	716559	0	0
T29	433507	433422	0	0
T30	18115	18026	0	0
T31	40615	40552	0	0
T32	307406	307340	0	0
T34	111861	111793	0	0