Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.56	98.77	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	744843	0	0
entropy_period_rd_A	2147483647	1410	0	0
intr_enable_rd_A	2147483647	2061	0	0
prefix_0_rd_A	2147483647	1255	0	0
prefix_10_rd_A	2147483647	1284	0	0
prefix_1_rd_A	2147483647	1216	0	0
prefix_2_rd_A	2147483647	1339	0	0
prefix_3_rd_A	2147483647	1429	0	0
prefix_4_rd_A	2147483647	1380	0	0
prefix_5_rd_A	2147483647	1316	0	0
prefix_6_rd_A	2147483647	1354	0	0
prefix_7_rd_A	2147483647	1382	0	0
prefix_8_rd_A	2147483647	1319	0	0
prefix_9_rd_A	2147483647	1299	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	744843	0	0
T43	827986	106183	0	0
T44	0	70819	0	0
T68	0	34107	0	0
T81	0	29200	0	0
T125	0	20280	0	0
T126	0	57769	0	0
T127	0	37325	0	0
T128	0	64672	0	0
T129	0	63311	0	0
T130	0	45869	0	0
T131	206335	0	0	0
T132	838418	0	0	0
T133	526689	0	0	0
T134	1452	0	0	0
T135	386061	0	0	0
T136	200834	0	0	0
T137	10045	0	0	0
T138	25076	0	0	0
T139	106779	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1410	0	0
T88	10647	26	0	0
T89	7235	57	0	0
T98	12484	64	0	0
T119	23973	123	0	0
T152	2036	3	0	0
T153	11932	43	0	0
T154	11856	12	0	0
T155	6662	34	0	0
T156	28518	242	0	0
T157	77259	90	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2061	0	0
T88	10647	37	0	0
T89	7235	35	0	0
T98	12484	96	0	0
T119	23973	170	0	0
T123	1469	5	0	0
T152	2036	1	0	0
T153	11932	37	0	0
T154	11856	41	0	0
T158	857	8	0	0
T159	1370	4	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1255	0	0
T88	10647	28	0	0
T89	7235	27	0	0
T94	2728	6	0	0
T98	12484	55	0	0
T119	23973	73	0	0
T152	2036	2	0	0
T153	11932	12	0	0
T154	11856	18	0	0
T155	6662	9	0	0
T160	3690	3	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1284	0	0
T88	10647	22	0	0
T89	7235	27	0	0
T94	2728	6	0	0
T98	12484	46	0	0
T119	23973	97	0	0
T152	2036	3	0	0
T153	11932	55	0	0
T154	11856	36	0	0
T155	6662	33	0	0
T160	3690	9	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1216	0	0
T88	10647	21	0	0
T89	7235	29	0	0
T98	12484	34	0	0
T119	23973	72	0	0
T153	11932	8	0	0
T154	11856	24	0	0
T155	6662	28	0	0
T156	28518	229	0	0
T157	77259	193	0	0
T161	39545	55	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1339	0	0
T88	10647	8	0	0
T89	7235	22	0	0
T94	2728	3	0	0
T98	12484	44	0	0
T119	23973	83	0	0
T152	2036	1	0	0
T153	11932	33	0	0
T154	11856	11	0	0
T155	6662	24	0	0
T160	3690	7	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1429	0	0
T88	10647	25	0	0
T89	7235	17	0	0
T94	2728	1	0	0
T98	12484	53	0	0
T119	23973	87	0	0
T152	2036	6	0	0
T153	11932	72	0	0
T154	11856	26	0	0
T155	6662	41	0	0
T160	3690	5	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1380	0	0
T88	10647	44	0	0
T89	7235	24	0	0
T98	12484	29	0	0
T119	23973	73	0	0
T152	2036	2	0	0
T153	11932	42	0	0
T154	11856	25	0	0
T155	6662	23	0	0
T156	28518	286	0	0
T157	77259	240	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1316	0	0
T88	10647	16	0	0
T89	7235	43	0	0
T98	12484	57	0	0
T119	23973	77	0	0
T153	11932	50	0	0
T154	11856	37	0	0
T155	6662	24	0	0
T156	28518	225	0	0
T157	77259	193	0	0
T160	3690	8	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1354	0	0
T88	10647	26	0	0
T89	7235	29	0	0
T98	12484	42	0	0
T119	23973	101	0	0
T152	2036	1	0	0
T153	11932	50	0	0
T154	11856	47	0	0
T155	6662	22	0	0
T156	28518	238	0	0
T160	3690	4	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1382	0	0
T88	10647	45	0	0
T89	7235	27	0	0
T98	12484	62	0	0
T119	23973	87	0	0
T152	2036	5	0	0
T153	11932	40	0	0
T154	11856	16	0	0
T155	6662	24	0	0
T156	28518	245	0	0
T160	3690	5	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1319	0	0
T88	10647	22	0	0
T89	7235	24	0	0
T98	12484	36	0	0
T119	23973	94	0	0
T152	2036	3	0	0
T153	11932	37	0	0
T154	11856	16	0	0
T155	6662	27	0	0
T156	28518	245	0	0
T160	3690	1	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1299	0	0
T88	10647	24	0	0
T89	7235	31	0	0
T98	12484	46	0	0
T119	23973	103	0	0
T153	11932	38	0	0
T154	11856	23	0	0
T155	6662	21	0	0
T156	28518	228	0	0
T157	77259	193	0	0
T161	39545	86	0	0