Unified Coverage Report :: Module :: kmac_reg_top

Module : kmac_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.87	100.00	99.46			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.87	100.00	99.46			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.87	100.00	99.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.98	99.39	96.55	100.00		98.93	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.55	98.71	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_fault_err	100.00	100.00
u_alert_test_recov_operation_err	100.00	100.00
u_cfg_regwen	100.00	100.00
u_cfg_shadowed0_qe	100.00	100.00				100.00
u_cfg_shadowed_en_unsupported_modestrength	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_entropy_fast_process	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_entropy_mode	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_entropy_ready	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_err_processed	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_kmac_en	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_kstrength	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_mode	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_msg_endianness	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_msg_mask	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_sideload	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_state_endianness	98.66	100.00	94.64			100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_cmd_cmd	100.00	100.00
u_cmd_entropy_req	100.00	100.00
u_cmd_hash_cnt_clr	100.00	100.00
u_entropy_period_prescaler	100.00	100.00	100.00			100.00
u_entropy_period_wait_timer	100.00	100.00	100.00			100.00
u_entropy_refresh_hash_cnt	62.59	77.78	50.00			60.00
u_entropy_refresh_threshold_shadowed	98.66	100.00	94.64			100.00	100.00
u_entropy_seed	100.00	100.00
u_err_code	100.00	100.00	100.00			100.00
u_intr_enable_fifo_empty	100.00	100.00	100.00			100.00
u_intr_enable_kmac_done	100.00	100.00	100.00			100.00
u_intr_enable_kmac_err	100.00	100.00	100.00			100.00
u_intr_state_fifo_empty	100.00	100.00	100.00			100.00
u_intr_state_kmac_done	100.00	100.00	100.00			100.00
u_intr_state_kmac_err	100.00	100.00	100.00			100.00
u_intr_test_fifo_empty	100.00	100.00
u_intr_test_kmac_done	100.00	100.00
u_intr_test_kmac_err	100.00	100.00
u_key_len	100.00	100.00	100.00			100.00
u_key_share0_0	100.00	100.00
u_key_share0_1	100.00	100.00
u_key_share0_10	100.00	100.00
u_key_share0_11	100.00	100.00
u_key_share0_12	100.00	100.00
u_key_share0_13	100.00	100.00
u_key_share0_14	100.00	100.00
u_key_share0_15	100.00	100.00
u_key_share0_2	100.00	100.00
u_key_share0_3	100.00	100.00
u_key_share0_4	100.00	100.00
u_key_share0_5	100.00	100.00
u_key_share0_6	100.00	100.00
u_key_share0_7	100.00	100.00
u_key_share0_8	100.00	100.00
u_key_share0_9	100.00	100.00
u_key_share1_0	100.00	100.00
u_key_share1_1	100.00	100.00
u_key_share1_10	100.00	100.00
u_key_share1_11	100.00	100.00
u_key_share1_12	100.00	100.00
u_key_share1_13	100.00	100.00
u_key_share1_14	100.00	100.00
u_key_share1_15	100.00	100.00
u_key_share1_2	100.00	100.00
u_key_share1_3	100.00	100.00
u_key_share1_4	100.00	100.00
u_key_share1_5	100.00	100.00
u_key_share1_6	100.00	100.00
u_key_share1_7	100.00	100.00
u_key_share1_8	100.00	100.00
u_key_share1_9	100.00	100.00
u_prefix_0	100.00	100.00	100.00			100.00
u_prefix_1	100.00	100.00	100.00			100.00
u_prefix_10	100.00	100.00	100.00			100.00
u_prefix_2	100.00	100.00	100.00			100.00
u_prefix_3	100.00	100.00	100.00			100.00
u_prefix_4	100.00	100.00	100.00			100.00
u_prefix_5	100.00	100.00	100.00			100.00
u_prefix_6	100.00	100.00	100.00			100.00
u_prefix_7	100.00	100.00	100.00			100.00
u_prefix_8	100.00	100.00	100.00			100.00
u_prefix_9	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.69	97.14	97.62			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_socket	91.58	96.18	82.65			87.50	100.00
u_status_alert_fatal_fault	100.00	100.00
u_status_alert_recov_ctrl_update_err	100.00	100.00
u_status_fifo_depth	100.00	100.00
u_status_fifo_empty	100.00	100.00
u_status_fifo_full	100.00	100.00
u_status_sha3_absorb	100.00	100.00
u_status_sha3_idle	100.00	100.00
u_status_sha3_squeeze	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : kmac_reg_top

	Line No.	Total	Covered	Percent
TOTAL		500	500	100.00
ALWAYS	77	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
ALWAYS	136	3	3	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	566	1	1	100.00
CONT_ASSIGN	582	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
CONT_ASSIGN	604	1	1	100.00
CONT_ASSIGN	619	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	668	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	778	1	1	100.00
CONT_ASSIGN	815	1	1	100.00
CONT_ASSIGN	852	1	1	100.00
CONT_ASSIGN	889	1	1	100.00
CONT_ASSIGN	926	1	1	100.00
CONT_ASSIGN	963	1	1	100.00
CONT_ASSIGN	1000	1	1	100.00
CONT_ASSIGN	1037	1	1	100.00
CONT_ASSIGN	1074	1	1	100.00
CONT_ASSIGN	1111	1	1	100.00
CONT_ASSIGN	1117	1	1	100.00
CONT_ASSIGN	1132	1	1	100.00
CONT_ASSIGN	1148	1	1	100.00
CONT_ASSIGN	1164	1	1	100.00
CONT_ASSIGN	1292	1	1	100.00
CONT_ASSIGN	1379	1	1	100.00
CONT_ASSIGN	1420	1	1	100.00
CONT_ASSIGN	1434	1	1	100.00
CONT_ASSIGN	1441	1	1	100.00
CONT_ASSIGN	1444	1	1	100.00
CONT_ASSIGN	1458	1	1	100.00
CONT_ASSIGN	1465	1	1	100.00
CONT_ASSIGN	1468	1	1	100.00
CONT_ASSIGN	1482	1	1	100.00
CONT_ASSIGN	1489	1	1	100.00
CONT_ASSIGN	1492	1	1	100.00
CONT_ASSIGN	1506	1	1	100.00
CONT_ASSIGN	1513	1	1	100.00
CONT_ASSIGN	1516	1	1	100.00
CONT_ASSIGN	1530	1	1	100.00
CONT_ASSIGN	1537	1	1	100.00
CONT_ASSIGN	1540	1	1	100.00
CONT_ASSIGN	1554	1	1	100.00
CONT_ASSIGN	1561	1	1	100.00
CONT_ASSIGN	1564	1	1	100.00
CONT_ASSIGN	1578	1	1	100.00
CONT_ASSIGN	1585	1	1	100.00
CONT_ASSIGN	1588	1	1	100.00
CONT_ASSIGN	1602	1	1	100.00
CONT_ASSIGN	1609	1	1	100.00
CONT_ASSIGN	1612	1	1	100.00
CONT_ASSIGN	1626	1	1	100.00
CONT_ASSIGN	1633	1	1	100.00
CONT_ASSIGN	1636	1	1	100.00
CONT_ASSIGN	1650	1	1	100.00
CONT_ASSIGN	1657	1	1	100.00
CONT_ASSIGN	1660	1	1	100.00
CONT_ASSIGN	1674	1	1	100.00
CONT_ASSIGN	1681	1	1	100.00
CONT_ASSIGN	1684	1	1	100.00
CONT_ASSIGN	1698	1	1	100.00
CONT_ASSIGN	1705	1	1	100.00
CONT_ASSIGN	1708	1	1	100.00
CONT_ASSIGN	1722	1	1	100.00
CONT_ASSIGN	1729	1	1	100.00
CONT_ASSIGN	1732	1	1	100.00
CONT_ASSIGN	1746	1	1	100.00
CONT_ASSIGN	1753	1	1	100.00
CONT_ASSIGN	1756	1	1	100.00
CONT_ASSIGN	1770	1	1	100.00
CONT_ASSIGN	1777	1	1	100.00
CONT_ASSIGN	1780	1	1	100.00
CONT_ASSIGN	1794	1	1	100.00
CONT_ASSIGN	1801	1	1	100.00
CONT_ASSIGN	1804	1	1	100.00
CONT_ASSIGN	1818	1	1	100.00
CONT_ASSIGN	1825	1	1	100.00
CONT_ASSIGN	1828	1	1	100.00
CONT_ASSIGN	1842	1	1	100.00
CONT_ASSIGN	1849	1	1	100.00
CONT_ASSIGN	1852	1	1	100.00
CONT_ASSIGN	1866	1	1	100.00
CONT_ASSIGN	1873	1	1	100.00
CONT_ASSIGN	1876	1	1	100.00
CONT_ASSIGN	1890	1	1	100.00
CONT_ASSIGN	1897	1	1	100.00
CONT_ASSIGN	1900	1	1	100.00
CONT_ASSIGN	1914	1	1	100.00
CONT_ASSIGN	1921	1	1	100.00
CONT_ASSIGN	1924	1	1	100.00
CONT_ASSIGN	1938	1	1	100.00
CONT_ASSIGN	1945	1	1	100.00
CONT_ASSIGN	1948	1	1	100.00
CONT_ASSIGN	1962	1	1	100.00
CONT_ASSIGN	1969	1	1	100.00
CONT_ASSIGN	1972	1	1	100.00
CONT_ASSIGN	1986	1	1	100.00
CONT_ASSIGN	1993	1	1	100.00
CONT_ASSIGN	1996	1	1	100.00
CONT_ASSIGN	2010	1	1	100.00
CONT_ASSIGN	2017	1	1	100.00
CONT_ASSIGN	2020	1	1	100.00
CONT_ASSIGN	2034	1	1	100.00
CONT_ASSIGN	2041	1	1	100.00
CONT_ASSIGN	2044	1	1	100.00
CONT_ASSIGN	2058	1	1	100.00
CONT_ASSIGN	2065	1	1	100.00
CONT_ASSIGN	2068	1	1	100.00
CONT_ASSIGN	2082	1	1	100.00
CONT_ASSIGN	2089	1	1	100.00
CONT_ASSIGN	2092	1	1	100.00
CONT_ASSIGN	2106	1	1	100.00
CONT_ASSIGN	2113	1	1	100.00
CONT_ASSIGN	2116	1	1	100.00
CONT_ASSIGN	2130	1	1	100.00
CONT_ASSIGN	2137	1	1	100.00
CONT_ASSIGN	2140	1	1	100.00
CONT_ASSIGN	2154	1	1	100.00
CONT_ASSIGN	2161	1	1	100.00
CONT_ASSIGN	2164	1	1	100.00
CONT_ASSIGN	2178	1	1	100.00
CONT_ASSIGN	2185	1	1	100.00
CONT_ASSIGN	2188	1	1	100.00
CONT_ASSIGN	2202	1	1	100.00
CONT_ASSIGN	2208	1	1	100.00
CONT_ASSIGN	2240	1	1	100.00
CONT_ASSIGN	2272	1	1	100.00
CONT_ASSIGN	2304	1	1	100.00
CONT_ASSIGN	2336	1	1	100.00
CONT_ASSIGN	2368	1	1	100.00
CONT_ASSIGN	2400	1	1	100.00
CONT_ASSIGN	2432	1	1	100.00
CONT_ASSIGN	2464	1	1	100.00
CONT_ASSIGN	2496	1	1	100.00
CONT_ASSIGN	2528	1	1	100.00
CONT_ASSIGN	2560	1	1	100.00
ALWAYS	2619	58	58	100.00
CONT_ASSIGN	2679	1	1	100.00
ALWAYS	2683	1	1	100.00
CONT_ASSIGN	2744	1	1	100.00
CONT_ASSIGN	2746	1	1	100.00
CONT_ASSIGN	2748	1	1	100.00
CONT_ASSIGN	2750	1	1	100.00
CONT_ASSIGN	2751	1	1	100.00
CONT_ASSIGN	2753	1	1	100.00
CONT_ASSIGN	2755	1	1	100.00
CONT_ASSIGN	2757	1	1	100.00
CONT_ASSIGN	2758	1	1	100.00
CONT_ASSIGN	2760	1	1	100.00
CONT_ASSIGN	2762	1	1	100.00
CONT_ASSIGN	2764	1	1	100.00
CONT_ASSIGN	2765	1	1	100.00
CONT_ASSIGN	2767	1	1	100.00
CONT_ASSIGN	2769	1	1	100.00
CONT_ASSIGN	2770	1	1	100.00
CONT_ASSIGN	2771	1	1	100.00
CONT_ASSIGN	2772	1	1	100.00
CONT_ASSIGN	2774	1	1	100.00
CONT_ASSIGN	2776	1	1	100.00
CONT_ASSIGN	2778	1	1	100.00
CONT_ASSIGN	2780	1	1	100.00
CONT_ASSIGN	2782	1	1	100.00
CONT_ASSIGN	2784	1	1	100.00
CONT_ASSIGN	2786	1	1	100.00
CONT_ASSIGN	2788	1	1	100.00
CONT_ASSIGN	2790	1	1	100.00
CONT_ASSIGN	2792	1	1	100.00
CONT_ASSIGN	2794	1	1	100.00
CONT_ASSIGN	2796	1	1	100.00
CONT_ASSIGN	2797	1	1	100.00
CONT_ASSIGN	2799	1	1	100.00
CONT_ASSIGN	2801	1	1	100.00
CONT_ASSIGN	2803	1	1	100.00
CONT_ASSIGN	2804	1	1	100.00
CONT_ASSIGN	2805	1	1	100.00
CONT_ASSIGN	2807	1	1	100.00
CONT_ASSIGN	2809	1	1	100.00
CONT_ASSIGN	2810	1	1	100.00
CONT_ASSIGN	2811	1	1	100.00
CONT_ASSIGN	2813	1	1	100.00
CONT_ASSIGN	2814	1	1	100.00
CONT_ASSIGN	2816	1	1	100.00
CONT_ASSIGN	2817	1	1	100.00
CONT_ASSIGN	2819	1	1	100.00
CONT_ASSIGN	2820	1	1	100.00
CONT_ASSIGN	2822	1	1	100.00
CONT_ASSIGN	2823	1	1	100.00
CONT_ASSIGN	2825	1	1	100.00
CONT_ASSIGN	2826	1	1	100.00
CONT_ASSIGN	2828	1	1	100.00
CONT_ASSIGN	2829	1	1	100.00
CONT_ASSIGN	2831	1	1	100.00
CONT_ASSIGN	2832	1	1	100.00
CONT_ASSIGN	2834	1	1	100.00
CONT_ASSIGN	2835	1	1	100.00
CONT_ASSIGN	2837	1	1	100.00
CONT_ASSIGN	2838	1	1	100.00
CONT_ASSIGN	2840	1	1	100.00
CONT_ASSIGN	2841	1	1	100.00
CONT_ASSIGN	2843	1	1	100.00
CONT_ASSIGN	2844	1	1	100.00
CONT_ASSIGN	2846	1	1	100.00
CONT_ASSIGN	2847	1	1	100.00
CONT_ASSIGN	2849	1	1	100.00
CONT_ASSIGN	2850	1	1	100.00
CONT_ASSIGN	2852	1	1	100.00
CONT_ASSIGN	2853	1	1	100.00
CONT_ASSIGN	2855	1	1	100.00
CONT_ASSIGN	2856	1	1	100.00
CONT_ASSIGN	2858	1	1	100.00
CONT_ASSIGN	2859	1	1	100.00
CONT_ASSIGN	2861	1	1	100.00
CONT_ASSIGN	2862	1	1	100.00
CONT_ASSIGN	2864	1	1	100.00
CONT_ASSIGN	2865	1	1	100.00
CONT_ASSIGN	2867	1	1	100.00
CONT_ASSIGN	2868	1	1	100.00
CONT_ASSIGN	2870	1	1	100.00
CONT_ASSIGN	2871	1	1	100.00
CONT_ASSIGN	2873	1	1	100.00
CONT_ASSIGN	2874	1	1	100.00
CONT_ASSIGN	2876	1	1	100.00
CONT_ASSIGN	2877	1	1	100.00
CONT_ASSIGN	2879	1	1	100.00
CONT_ASSIGN	2880	1	1	100.00
CONT_ASSIGN	2882	1	1	100.00
CONT_ASSIGN	2883	1	1	100.00
CONT_ASSIGN	2885	1	1	100.00
CONT_ASSIGN	2886	1	1	100.00
CONT_ASSIGN	2888	1	1	100.00
CONT_ASSIGN	2889	1	1	100.00
CONT_ASSIGN	2891	1	1	100.00
CONT_ASSIGN	2892	1	1	100.00
CONT_ASSIGN	2894	1	1	100.00
CONT_ASSIGN	2895	1	1	100.00
CONT_ASSIGN	2897	1	1	100.00
CONT_ASSIGN	2898	1	1	100.00
CONT_ASSIGN	2900	1	1	100.00
CONT_ASSIGN	2901	1	1	100.00
CONT_ASSIGN	2903	1	1	100.00
CONT_ASSIGN	2904	1	1	100.00
CONT_ASSIGN	2906	1	1	100.00
CONT_ASSIGN	2907	1	1	100.00
CONT_ASSIGN	2909	1	1	100.00
CONT_ASSIGN	2910	1	1	100.00
CONT_ASSIGN	2912	1	1	100.00
CONT_ASSIGN	2913	1	1	100.00
CONT_ASSIGN	2915	1	1	100.00
CONT_ASSIGN	2916	1	1	100.00
CONT_ASSIGN	2918	1	1	100.00
CONT_ASSIGN	2919	1	1	100.00
CONT_ASSIGN	2921	1	1	100.00
CONT_ASSIGN	2922	1	1	100.00
CONT_ASSIGN	2924	1	1	100.00
CONT_ASSIGN	2925	1	1	100.00
CONT_ASSIGN	2927	1	1	100.00
CONT_ASSIGN	2928	1	1	100.00
CONT_ASSIGN	2930	1	1	100.00
CONT_ASSIGN	2931	1	1	100.00
CONT_ASSIGN	2933	1	1	100.00
CONT_ASSIGN	2934	1	1	100.00
CONT_ASSIGN	2936	1	1	100.00
CONT_ASSIGN	2937	1	1	100.00
CONT_ASSIGN	2939	1	1	100.00
CONT_ASSIGN	2940	1	1	100.00
CONT_ASSIGN	2942	1	1	100.00
CONT_ASSIGN	2943	1	1	100.00
CONT_ASSIGN	2945	1	1	100.00
CONT_ASSIGN	2946	1	1	100.00
CONT_ASSIGN	2948	1	1	100.00
ALWAYS	2952	58	58	100.00
ALWAYS	3014	87	87	100.00
ALWAYS	3283	3	3	100.00
ALWAYS	3291	3	3	100.00
CONT_ASSIGN	3299	1	1	100.00
CONT_ASSIGN	3302	1	1	100.00
CONT_ASSIGN	3317	1	1	100.00
CONT_ASSIGN	3334	1	1	100.00
CONT_ASSIGN	3342	1	1	100.00
CONT_ASSIGN	3343	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
77	1	1
78	1	1
79	1	1
80	1	1
			MISSING_ELSE
86	1	1
104	1	1
105	1	1
107	1	1
108	1	1
109	1	1
110	1	1
136	1	1
143	1	1
144	1	1
			MISSING_ELSE
174	1	1
175	1	1
551	1	1
566	1	1
582	1	1
598	1	1
604	1	1
619	1	1
635	1	1
668	1	1
704	1	1
741	1	1
778	1	1
815	1	1
852	1	1
889	1	1
926	1	1
963	1	1
1000	1	1
1037	1	1
1074	1	1
1111	1	1
1117	1	1
1132	1	1
1148	1	1
1164	1	1
1292	1	1
1379	1	1
1420	1	1
1434	1	1
1441	1	1
1444	1	1
1458	1	1
1465	1	1
1468	1	1
1482	1	1
1489	1	1
1492	1	1
1506	1	1
1513	1	1
1516	1	1
1530	1	1
1537	1	1
1540	1	1
1554	1	1
1561	1	1
1564	1	1
1578	1	1
1585	1	1
1588	1	1
1602	1	1
1609	1	1
1612	1	1
1626	1	1
1633	1	1
1636	1	1
1650	1	1
1657	1	1
1660	1	1
1674	1	1
1681	1	1
1684	1	1
1698	1	1
1705	1	1
1708	1	1
1722	1	1
1729	1	1
1732	1	1
1746	1	1
1753	1	1
1756	1	1
1770	1	1
1777	1	1
1780	1	1
1794	1	1
1801	1	1
1804	1	1
1818	1	1
1825	1	1
1828	1	1
1842	1	1
1849	1	1
1852	1	1
1866	1	1
1873	1	1
1876	1	1
1890	1	1
1897	1	1
1900	1	1
1914	1	1
1921	1	1
1924	1	1
1938	1	1
1945	1	1
1948	1	1
1962	1	1
1969	1	1
1972	1	1
1986	1	1
1993	1	1
1996	1	1
2010	1	1
2017	1	1
2020	1	1
2034	1	1
2041	1	1
2044	1	1
2058	1	1
2065	1	1
2068	1	1
2082	1	1
2089	1	1
2092	1	1
2106	1	1
2113	1	1
2116	1	1
2130	1	1
2137	1	1
2140	1	1
2154	1	1
2161	1	1
2164	1	1
2178	1	1
2185	1	1
2188	1	1
2202	1	1
2208	1	1
2240	1	1
2272	1	1
2304	1	1
2336	1	1
2368	1	1
2400	1	1
2432	1	1
2464	1	1
2496	1	1
2528	1	1
2560	1	1
2619	1	1
2620	1	1
2621	1	1
2622	1	1
2623	1	1
2624	1	1
2625	1	1
2626	1	1
2627	1	1
2628	1	1
2629	1	1
2630	1	1
2631	1	1
2632	1	1
2633	1	1
2634	1	1
2635	1	1
2636	1	1
2637	1	1
2638	1	1
2639	1	1
2640	1	1
2641	1	1
2642	1	1
2643	1	1
2644	1	1
2645	1	1
2646	1	1
2647	1	1
2648	1	1
2649	1	1
2650	1	1
2651	1	1
2652	1	1
2653	1	1
2654	1	1
2655	1	1
2656	1	1
2657	1	1
2658	1	1
2659	1	1
2660	1	1
2661	1	1
2662	1	1
2663	1	1
2664	1	1
2665	1	1
2666	1	1
2667	1	1
2668	1	1
2669	1	1
2670	1	1
2671	1	1
2672	1	1
2673	1	1
2674	1	1
2675	1	1
2676	1	1
2679	1	1
2683	1	1
2744	1	1
2746	1	1
2748	1	1
2750	1	1
2751	1	1
2753	1	1
2755	1	1
2757	1	1
2758	1	1
2760	1	1
2762	1	1
2764	1	1
2765	1	1
2767	1	1
2769	1	1
2770	1	1
2771	1	1
2772	1	1
2774	1	1
2776	1	1
2778	1	1
2780	1	1
2782	1	1
2784	1	1
2786	1	1
2788	1	1
2790	1	1
2792	1	1
2794	1	1
2796	1	1
2797	1	1
2799	1	1
2801	1	1
2803	1	1
2804	1	1
2805	1	1
2807	1	1
2809	1	1
2810	1	1
2811	1	1
2813	1	1
2814	1	1
2816	1	1
2817	1	1
2819	1	1
2820	1	1
2822	1	1
2823	1	1
2825	1	1
2826	1	1
2828	1	1
2829	1	1
2831	1	1
2832	1	1
2834	1	1
2835	1	1
2837	1	1
2838	1	1
2840	1	1
2841	1	1
2843	1	1
2844	1	1
2846	1	1
2847	1	1
2849	1	1
2850	1	1
2852	1	1
2853	1	1
2855	1	1
2856	1	1
2858	1	1
2859	1	1
2861	1	1
2862	1	1
2864	1	1
2865	1	1
2867	1	1
2868	1	1
2870	1	1
2871	1	1
2873	1	1
2874	1	1
2876	1	1
2877	1	1
2879	1	1
2880	1	1
2882	1	1
2883	1	1
2885	1	1
2886	1	1
2888	1	1
2889	1	1
2891	1	1
2892	1	1
2894	1	1
2895	1	1
2897	1	1
2898	1	1
2900	1	1
2901	1	1
2903	1	1
2904	1	1
2906	1	1
2907	1	1
2909	1	1
2910	1	1
2912	1	1
2913	1	1
2915	1	1
2916	1	1
2918	1	1
2919	1	1
2921	1	1
2922	1	1
2924	1	1
2925	1	1
2927	1	1
2928	1	1
2930	1	1
2931	1	1
2933	1	1
2934	1	1
2936	1	1
2937	1	1
2939	1	1
2940	1	1
2942	1	1
2943	1	1
2945	1	1
2946	1	1
2948	1	1
2952	1	1
2953	1	1
2954	1	1
2955	1	1
2956	1	1
2957	1	1
2958	1	1
2959	1	1
2960	1	1
2961	1	1
2962	1	1
2963	1	1
2964	1	1
2965	1	1
2966	1	1
2967	1	1
2968	1	1
2969	1	1
2970	1	1
2971	1	1
2972	1	1
2973	1	1
2974	1	1
2975	1	1
2976	1	1
2977	1	1
2978	1	1
2979	1	1
2980	1	1
2981	1	1
2982	1	1
2983	1	1
2984	1	1
2985	1	1
2986	1	1
2987	1	1
2988	1	1
2989	1	1
2990	1	1
2991	1	1
2992	1	1
2993	1	1
2994	1	1
2995	1	1
2996	1	1
2997	1	1
2998	1	1
2999	1	1
3000	1	1
3001	1	1
3002	1	1
3003	1	1
3004	1	1
3005	1	1
3006	1	1
3007	1	1
3008	1	1
3009	1	1
3014	1	1
3015	1	1
3017	1	1
3018	1	1
3019	1	1
3023	1	1
3024	1	1
3025	1	1
3029	1	1
3030	1	1
3031	1	1
3035	1	1
3036	1	1
3040	1	1
3044	1	1
3045	1	1
3046	1	1
3047	1	1
3048	1	1
3049	1	1
3050	1	1
3051	1	1
3052	1	1
3053	1	1
3054	1	1
3055	1	1
3059	1	1
3060	1	1
3061	1	1
3065	1	1
3066	1	1
3067	1	1
3068	1	1
3069	1	1
3070	1	1
3071	1	1
3072	1	1
3076	1	1
3077	1	1
3081	1	1
3085	1	1
3089	1	1
3093	1	1
3097	1	1
3101	1	1
3105	1	1
3109	1	1
3113	1	1
3117	1	1
3121	1	1
3125	1	1
3129	1	1
3133	1	1
3137	1	1
3141	1	1
3145	1	1
3149	1	1
3153	1	1
3157	1	1
3161	1	1
3165	1	1
3169	1	1
3173	1	1
3177	1	1
3181	1	1
3185	1	1
3189	1	1
3193	1	1
3197	1	1
3201	1	1
3205	1	1
3209	1	1
3213	1	1
3217	1	1
3221	1	1
3225	1	1
3229	1	1
3233	1	1
3237	1	1
3241	1	1
3245	1	1
3249	1	1
3253	1	1
3257	1	1
3261	1	1
3265	1	1
3269	1	1
3283	1	1
3284	1	1
3286	1	1
3291	1	1
3292	1	1
3294	1	1
3299	1	1
3302	1	1
3317	1	1
3334	1	1
3342	1	1
3343	1	1

---

Cond Coverage for Module : kmac_reg_top

	Total	Covered	Percent
Conditions	741	737	99.46
Logical	741	737	99.46
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
67-2683	100.00
2683-3299	98.78

---

Branch Coverage for Module : kmac_reg_top

	Line No.	Total	Covered	Percent
Branches		72	72	100.00
TERNARY	2679	2	2	100.00
IF	77	3	3	100.00
TERNARY	136	3	3	100.00
IF	143	2	2	100.00
CASE	3015	58	58	100.00
IF	3283	2	2	100.00
IF	3291	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	2679	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if ((!rst_ni))
-2-:	79	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	136	((tl_i.a_address[(AW - 1):0] inside {[1024:1535]})) ? 
-2-:	136	((tl_i.a_address[(AW - 1):0] inside {[2048:4095]})) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	143	if (intg_err)

Branches:

-1-	Status	Tests
1	Covered	T122,T123,T124
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3015	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T2,T3,T7
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
addr_hit[35]	Covered	T1,T2,T3
addr_hit[36]	Covered	T1,T2,T3
addr_hit[37]	Covered	T1,T2,T3
addr_hit[38]	Covered	T1,T2,T3
addr_hit[39]	Covered	T1,T2,T3
addr_hit[40]	Covered	T1,T2,T3
addr_hit[41]	Covered	T1,T2,T3
addr_hit[42]	Covered	T1,T2,T3
addr_hit[43]	Covered	T1,T2,T3
addr_hit[44]	Covered	T1,T2,T3
addr_hit[45]	Covered	T1,T2,T3
addr_hit[46]	Covered	T1,T2,T3
addr_hit[47]	Covered	T1,T2,T3
addr_hit[48]	Covered	T1,T2,T3
addr_hit[49]	Covered	T1,T2,T3
addr_hit[50]	Covered	T1,T2,T3
addr_hit[51]	Covered	T1,T2,T3
addr_hit[52]	Covered	T1,T2,T3
addr_hit[53]	Covered	T1,T2,T3
addr_hit[54]	Covered	T1,T2,T3
addr_hit[55]	Covered	T1,T2,T3
addr_hit[56]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3283	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3291	if ((!rst_shadowed_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : kmac_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	2147483647	309014905	0	0
reAfterRv	2147483647	309014905	0	0
rePulse	2147483647	204386468	0	0
wePulse	2147483647	104628437	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	309014905	0	0
T1	22278	1414	0	0
T2	380372	4435	0	0
T3	212276	565952	0	0
T7	20475	1314	0	0
T8	546477	17742	0	0
T9	23516	847	0	0
T22	377395	12543	0	0
T23	201730	635473	0	0
T24	105556	338028	0	0
T25	357204	54363	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	309014905	0	0
T1	22278	1414	0	0
T2	380372	4435	0	0
T3	212276	565952	0	0
T7	20475	1314	0	0
T8	546477	17742	0	0
T9	23516	847	0	0
T22	377395	12543	0	0
T23	201730	635473	0	0
T24	105556	338028	0	0
T25	357204	54363	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	204386468	0	0
T1	22278	565	0	0
T2	380372	553	0	0
T3	212276	409825	0	0
T7	20475	555	0	0
T8	546477	11028	0	0
T9	23516	451	0	0
T22	377395	3283	0	0
T23	201730	418751	0	0
T24	105556	222135	0	0
T25	357204	37951	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	104628437	0	0
T1	22278	849	0	0
T2	380372	3882	0	0
T3	212276	156127	0	0
T7	20475	759	0	0
T8	546477	6714	0	0
T9	23516	396	0	0
T22	377395	9260	0	0
T23	201730	216722	0	0
T24	105556	115893	0	0
T25	357204	16412	0	0