Unified Coverage Report :: Module :: kmac

Module : kmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.55	98.71	96.05	100.00	100.00	96.55	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	98.55	98.71	96.05	100.00	100.00	96.55	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.55	98.71	96.05	100.00	100.00	96.55	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.99	98.15	92.62	99.89	96.36	96.04	98.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
gen_entropy.u_entropy	97.83	100.00	87.97	100.00	100.00	98.98	100.00
gen_entropy.u_prim_sync_reqack_data	95.83	100.00	83.33			100.00	100.00
intr_fifo_empty	93.75	100.00	75.00			100.00	100.00
intr_kmac_done	93.75	100.00	75.00			100.00	100.00
intr_kmac_err	93.75	100.00	75.00			100.00	100.00
kmac_csr_assert	100.00						100.00
sha3pad_assert_cov_if	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_app_intf	97.42	97.45	90.82		100.00	98.82	100.00
u_errchk	96.60	95.06	94.59		100.00	93.33	100.00
u_kmac_core	95.80	98.88	92.86	100.00	100.00	91.38	91.67
u_msgfifo	97.32	100.00	95.16	94.52	100.00	94.23	100.00
u_prim_lc_sync	100.00	100.00				100.00	100.00
u_reg	98.98	99.39	96.55	100.00		98.93	100.00
u_sha3	96.94	98.84	95.67	100.00	90.48	96.64	100.00
u_sha3_done_sender	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00
u_staterd	89.71	89.72	80.83			88.30	100.00
u_tlul_adapter_msgfifo	79.67	86.78	73.83			76.83	81.25

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : kmac

	Line No.	Total	Covered	Percent
TOTAL		155	153	98.71
ALWAYS	343	0	0
ALWAYS	343	2	2	100.00
ALWAYS	349	1	0	0.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
ALWAYS	426	9	9	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
ALWAYS	485	6	6	100.00
ALWAYS	498	6	6	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	540	1	1	100.00
CONT_ASSIGN	542	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
ALWAYS	558	5	5	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
CONT_ASSIGN	576	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
ALWAYS	607	3	3	100.00
CONT_ASSIGN	611	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
ALWAYS	638	7	7	100.00
CONT_ASSIGN	674	1	1	100.00
CONT_ASSIGN	679	1	1	100.00
CONT_ASSIGN	686	1	1	100.00
CONT_ASSIGN	696	1	1	100.00
ALWAYS	716	3	3	100.00
ALWAYS	720	28	28	100.00
ALWAYS	858	3	3	100.00
CONT_ASSIGN	866	1	1	100.00
CONT_ASSIGN	866	1	1	100.00
CONT_ASSIGN	938	1	1	100.00
CONT_ASSIGN	940	1	1	100.00
CONT_ASSIGN	970	1	1	100.00
CONT_ASSIGN	975	1	1	100.00
CONT_ASSIGN	976	1	1	100.00
CONT_ASSIGN	978	1	1	100.00
CONT_ASSIGN	981	0	0
ALWAYS	1099	0	0
ALWAYS	1099	2	2	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1328	1	1	100.00
CONT_ASSIGN	1342	1	1	100.00
CONT_ASSIGN	1349	1	1	100.00
CONT_ASSIGN	1354	1	1	100.00
ALWAYS	1360	6	5	83.33
CONT_ASSIGN	1369	1	1	100.00
CONT_ASSIGN	1371	1	1	100.00
ALWAYS	1383	4	4	100.00
CONT_ASSIGN	1389	1	1	100.00
ALWAYS	1412	4	4	100.00
ALWAYS	1422	3	3	100.00
CONT_ASSIGN	1433	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00
CONT_ASSIGN	1439	1	1	100.00
CONT_ASSIGN	1439	1	1	100.00
CONT_ASSIGN	1439	1	1	100.00
CONT_ASSIGN	1439	1	1	100.00
CONT_ASSIGN	1439	1	1	100.00
CONT_ASSIGN	1439	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
343	1	1
344	1	1
349	0	1
418	1	1
419	1	1
423	1	1
426	1	1
427	1	1
428	1	1
429	1	1
431	1	1
433	1	1
437	1	1
441	1	1
445	1	1
461	1	1
462	1	1
463	1	1
466	1	1
470	1	1
471	1	1
475	1	1
478	1	1
485	1	1
486	1	1
487	1	1
488	1	1
489	1	1
490	1	1
			MISSING_ELSE
			MISSING_ELSE
498	1	1
499	1	1
500	1	1
501	1	1
502	1	1
503	1	1
			MISSING_ELSE
			MISSING_ELSE
515	1	1
522	1	1
525	1	1
526	1	1
527	1	1
529	1	1
530	1	1
532	1	1
534	1	1
536	1	1
540	1	1
542	1	1
543	1	1
546	1	1
547	1	1
550	1	1
558	1	1
559	1	1
560	1	1
561	1	1
563	1	1
568	1	1
575	1	1
576	1	1
577	1	1
587	1	1
607	2	2
608	1	1
611	1	1
630	1	1
635	1	1
638	1	1
640	1	1
645	1	1
649	1	1
653	1	1
657	1	1
661	1	1
674	1	1
679	1	1
686	1	1
696	1	1
716	3	3
720	1	1
722	1	1
723	1	1
725	1	1
727	1	1
729	1	1
730	1	1
733	1	1
736	1	1
742	1	1
743	1	1
745	1	1
750	1	1
751	1	1
752	1	1
754	1	1
760	1	1
765	1	1
766	1	1
768	1	1
770	1	1
776	1	1
777	1	1
779	1	1
785	1	1
786	1	1
798	1	1
799	1	1
			MISSING_ELSE
858	1	1
859	1	1
861	1	1
866	2	2
938	1	1
940	1	1
970	1	1
975	1	1
976	1	1
978	1	1
981		unreachable
1099	1	1
1100	1	1
1185	1	1
1328	1	1
1342	1	1
1349	1	1
1354	1	1
1360	1	1
1361	1	1
1362	1	1
1363	0	1
1364	1	1
1365	1	1
			MISSING_ELSE
1369	1	1
1371	1	1
1383	1	1
1384	1	1
1385	1	1
1386	1	1
			MISSING_ELSE
1389	1	1
1412	1	1
1413	1	1
1414	1	1
1416	1	1
			MISSING_ELSE
1422	1	1
1423	1	1
1426	1	1
1433	1	1
1437	1	1
1439	6	6

---

Cond Coverage for Module : kmac

	Total	Covered	Percent
Conditions	76	73	96.05
Logical	76	73	96.05
Non-Logical	0	0
Event	0	0

 LINE       423
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       461
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       462
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       463
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       475
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       527
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T27,T57,T58

 LINE       536
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T27,T57,T13

 LINE       540
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T44,T45
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       547
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       560
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6
1	1	Covered	T1,T2,T3

 LINE       560
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       560
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

 LINE       568
 EXPRESSION (reg2hw.cfg_shadowed.err_processed.q & reg2hw.cfg_shadowed.err_processed.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T44,T45,T49
1	1	Covered	T44,T45,T49

 LINE       611
 EXPRESSION (((~msgfifo_empty_q)) & msgfifo_empty)
             ----------1---------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       630
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T78,T79,T80
0	0	1	0	Covered	T69,T70,T71
0	1	0	0	Covered	T9,T10,T44
1	0	0	0	Covered	T3,T13,T14

 LINE       674
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T4,T5,T6
0	0	1	0	Covered	T4,T5,T6
0	1	0	0	Covered	T4,T5,T6
1	0	0	0	Covered	T4,T5,T6

 LINE       686
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T4,T5,T6
0	0	0	0	1	0	Covered	T4,T5,T6
0	0	0	1	0	0	Covered	T4,T5,T6
0	0	1	0	0	0	Covered	T4,T5,T6
0	1	0	0	0	0	Covered	T4,T5,T6
1	0	0	0	0	0	Covered	T4,T5,T6

 LINE       727
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       729
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T3,T22,T8
1	Covered	T1,T2,T3

 LINE       743
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T1,T3,T7

 LINE       970
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Not Covered
1	1	Covered	T1,T3,T7

 LINE       1100
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       1342
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T100,T101,T102
1	0	Covered	T1,T2,T3
1	1	Covered	T100,T101,T102

 LINE       1342
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T100,T101,T102
1	0	Covered	T1,T2,T3
1	1	Covered	T100,T101,T102

 LINE       1371
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T4,T5,T6
0	0	1	0	0	Covered	T9,T10,T11
0	1	0	0	0	Covered	T4,T5,T6
1	0	0	0	0	Not Covered

---

Toggle Coverage for Module : kmac

	Total	Covered	Percent
Totals	71	71	100.00
Total Bits	6534	6534	100.00
Total Bits 0->1	3267	3267	100.00
Total Bits 1->0	3267	3267	100.00

Ports	71	71	100.00
Port Bits	6534	6534	100.00
Port Bits 0->1	3267	3267	100.00
Port Bits 1->0	3267	3267	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T9,T27	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T3,T9,T27	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T3,T9,T27	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T22	Yes	T1,T3,T22	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T13,T20,T21	Yes	T13,T20,T21	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T100,T101,T102	Yes	T100,T101,T102	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T100,T101,T102	Yes	T100,T101,T102	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	OUTPUT
keymgr_key_i.key[0][4:0]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][5]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][10:6]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][11]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][15:12]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][16]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][21:17]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][23:22]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][29:24]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][30]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][33:31]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][34]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][37:35]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][38]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][49:39]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][50]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][53:51]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][54]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][56:55]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][57]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][58]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][60:59]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][61]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][63:62]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][70:64]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][71]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][72]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][73]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][74]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][76:75]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][77]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][79:78]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][81:80]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][82]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][83]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][85:84]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][86]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][87]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][88]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][89]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][93:90]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][95:94]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][98:96]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][100:99]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][102:101]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][103]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][105:104]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][106]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][107]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][108]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][115:109]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][116]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][119:117]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][120]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][128:121]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][131:129]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][134:132]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][135]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][137:136]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][138]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][144:139]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][146:145]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][153:147]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][154]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][160:155]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][161]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][165:162]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][166]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][168:167]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][170:169]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][177:171]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][178]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][179]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][180]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][182:181]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][183]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][190:184]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][191]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][205:192]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][206]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][207]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][208]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][219:209]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][220]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][221]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][223:222]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][224]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][225]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][226]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][229:227]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][239:230]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][241:240]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][243:242]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][245:244]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][249:246]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][251:250]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][253:252]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][254]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[0][255]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][2:0]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][4:3]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][12:5]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][13]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][14]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][15]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][18:16]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][19]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][23:20]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][24]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][27:25]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][28]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][30:29]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][31]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][33:32]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][34]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][37:35]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][38]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][48:39]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][49]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][50]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][51]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][53:52]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][54]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][62:55]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][63]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][64]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][67:65]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][69:68]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][70]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][75:71]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][79:76]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][86:80]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][87]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][90:88]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][92:91]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][95:93]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][96]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][100:97]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][101]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][102]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][103]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][108:104]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][109]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][112:110]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][113]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][121:114]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][122]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][124:123]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][125]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][128:126]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][129]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][130]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][131]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][137:132]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][138]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][140:139]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][141]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][146:142]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][149:147]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][152:150]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][153]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][155:154]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][157:156]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][163:158]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][170:164]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][182:171]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][183]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][198:184]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][199]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][200]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][201]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][203:202]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][205:204]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][206]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][207]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][208]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][209]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][215:210]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][216]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][220:217]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][221]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][223:222]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][224]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][225]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][226]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][230:227]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][231]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][233:232]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][234]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][243:235]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][244]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][247:245]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][248]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][254:249]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.key[1][255]	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
keymgr_key_i.valid	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
app_i[0].last	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	INPUT
app_i[0].strb[7:0]	Yes	Yes	T8,T27,T29	Yes	T8,T27,T29	INPUT
app_i[0].data[63:0]	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	INPUT
app_i[0].valid	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	INPUT
app_i[1].last	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	INPUT
app_i[1].strb[7:0]	Yes	Yes	T8,T27,T29	Yes	T8,T27,T29	INPUT
app_i[1].data[63:0]	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	INPUT
app_i[1].valid	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	INPUT
app_i[2].last	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	INPUT
app_i[2].strb[7:0]	Yes	Yes	T8,T27,T29	Yes	T8,T27,T29	INPUT
app_i[2].data[63:0]	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	INPUT
app_i[2].valid	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	INPUT
app_o[0].error	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	OUTPUT
app_o[0].digest_share1[383:0]	Yes	Yes	T3,T8,T25	Yes	T3,T8,T25	OUTPUT
app_o[0].digest_share0[383:0]	Yes	Yes	T3,T8,T9	Yes	T3,T8,T9	OUTPUT
app_o[0].done	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	OUTPUT
app_o[0].ready	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	OUTPUT
app_o[1].error	Yes	Yes	T3,T33,T13	Yes	T3,T33,T13	OUTPUT
app_o[1].digest_share1[383:0]	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	OUTPUT
app_o[1].digest_share0[383:0]	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	OUTPUT
app_o[1].done	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	OUTPUT
app_o[1].ready	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	OUTPUT
app_o[2].error	Yes	Yes	T3,T9,T32	Yes	T3,T9,T32	OUTPUT
app_o[2].digest_share1[383:0]	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	OUTPUT
app_o[2].digest_share0[383:0]	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	OUTPUT
app_o[2].done	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	OUTPUT
app_o[2].ready	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	OUTPUT
entropy_o.edn_req	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	OUTPUT
entropy_i.edn_bus[31:0]	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	INPUT
entropy_i.edn_fips	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	INPUT
entropy_i.edn_ack	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T9,T10,T32	Yes	T9,T10,T32	INPUT
intr_kmac_done_o	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
intr_fifo_empty_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_kmac_err_o	Yes	Yes	T3,T9,T10	Yes	T3,T9,T10	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : kmac

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	768	Covered	T1,T3,T7
KmacIdle	736	Covered	T1,T2,T3
KmacKeyBlock	743	Covered	T1,T3,T7
KmacMsgFeed	733	Covered	T1,T2,T3
KmacPrefix	730	Covered	T1,T2,T3
KmacTerminalError	785	Covered	T9,T10,T11

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	777	Covered	T1,T3,T7
KmacDigest->KmacTerminalError	799	Covered	T12
KmacIdle->KmacMsgFeed	733	Covered	T3,T22,T8
KmacIdle->KmacPrefix	730	Covered	T1,T2,T3
KmacIdle->KmacTerminalError	799	Covered	T4,T5,T6
KmacKeyBlock->KmacMsgFeed	752	Covered	T1,T3,T7
KmacKeyBlock->KmacTerminalError	799	Covered	T10,T41,T43
KmacMsgFeed->KmacDigest	768	Covered	T1,T3,T7
KmacMsgFeed->KmacIdle	765	Covered	T2,T3,T8
KmacMsgFeed->KmacTerminalError	799	Covered	T9,T32,T33
KmacPrefix->KmacKeyBlock	743	Covered	T1,T3,T7
KmacPrefix->KmacMsgFeed	743	Covered	T2,T3,T8
KmacPrefix->KmacTerminalError	799	Covered	T11,T37,T42

---

Branch Coverage for Module : kmac

	Line No.	Total	Covered	Percent
Branches		58	56	96.55
TERNARY	423	2	2	100.00
CASE	431	6	5	83.33
IF	485	3	3	100.00
IF	558	3	3	100.00
IF	607	2	2	100.00
CASE	640	6	6	100.00
IF	716	2	2	100.00
CASE	725	15	15	100.00
IF	798	2	2	100.00
TERNARY	1100	2	2	100.00
IF	1360	4	3	75.00
IF	1383	3	3	100.00
IF	1412	3	3	100.00
IF	1422	2	2	100.00
IF	498	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	423	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	431	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Covered	T1,T2,T3
CmdProcess	Covered	T1,T2,T3
CmdManualRun	Covered	T3,T8,T9
CmdDone	Covered	T1,T2,T3
CmdNone	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	485	if ((!rst_ni))
-2-:	487	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	558	if ((!rst_ni))
-2-:	560	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	607	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	640	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Covered	T9,T10,T44
errchecker_err.valid	Covered	T78,T79,T80
sha3_err.valid	Covered	T3,T13,T14
entropy_err.valid	Covered	T69,T70,T71
msgfifo_err.valid	Covered	T4,T5,T6
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	716	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	725	case (kmac_st)
-2-:	727	if ((kmac_cmd == CmdStart))
-3-:	729	if ((CShake == app_sha3_mode))
-4-:	742	if (sha3_block_processed)
-5-:	743	(app_kmac_en) ? 
-6-:	751	if (sha3_block_processed)
-7-:	760	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	766	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	776	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
KmacIdle	1	0	-	-	-	-	-	-	Covered	T3,T22,T8
KmacIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T1,T3,T7
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T2,T3,T8
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T1,T3,T7
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T1,T3,T7
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T2,T3,T8
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T1,T3,T7
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	1	Covered	T1,T3,T7
KmacDigest	-	-	-	-	-	-	-	0	Covered	T1,T3,T7
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	798	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1100	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1360	if ((!rst_ni))
-2-:	1362	if (alert_recov_operation)
-3-:	1364	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T44,T45,T49
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1383	if ((!rst_ni))
-2-:	1385	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1412	if ((!rst_ni))
-2-:	1414	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1422	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	498	if ((!rst_ni))
-2-:	500	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	35	35	100.00	35	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	35	35	100.00	35	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	2147483647	2147483647	0	0
CmdSparse_M	2147483647	1242986	0	0
EnMaskingKnown_A	2147483647	2147483647	0	0
EntropyReadyLatched_A	2147483647	327444	0	0
EntrySizeRegSameToEntrySizePkg_A	1013	1013	0	0
ErrProcessedLatched_A	2147483647	706	0	0
FifoEmpty_A	2147483647	2147483647	0	0
FpvSecCmErrorCheckFsmCheck_A	2147483647	80	0	0
FpvSecCmKeccackFsmCheck_A	2147483647	80	0	0
FpvSecCmKeyIndexCountCheck_A	2147483647	80	0	0
FpvSecCmKmacAppFsmCheck_A	2147483647	80	0	0
FpvSecCmKmacCoreFsmCheck_A	2147483647	80	0	0
FpvSecCmKmacFsmCheck_A	2147483647	80	0	0
FpvSecCmRegWeOnehotCheck_A	2147483647	80	0	0
FpvSecCmRoundCountCheck_A	2147483647	80	0	0
FpvSecCmSHA3FsmCheck_A	2147483647	80	0	0
FpvSecCmSHA3padFsmCheck_A	2147483647	80	0	0
FpvSecCmSentMsgCountCheck_A	2147483647	80	0	0
KmacCmd_A	2147483647	2147483647	0	0
KmacDone_A	2147483647	2147483647	0	0
KmacErr_A	2147483647	2147483647	0	0
KmacStKnown_A	2147483647	2147483647	0	0
NumAlerts2_A	1013	1013	0	0
NumEntriesRegSameToNumEntriesPkg_A	1013	1013	0	0
PrefixRegSameToPrefixPkg_A	1013	1013	0	0
SecretKeyDivideBy32_A	1013	1013	0	0
Sha3AbsorbedPulse_A	2147483647	336043	0	0
TlOAReadyKnown_A	2147483647	2147483647	0	0
TlODValidKnown_A	2147483647	2147483647	0	0
g_testassertion.FpvSecCmEntropyFsmCheck_A	2147483647	80	0	0
g_testassertion.FpvSecCmHashCountCheck_A	2147483647	80	0	0
g_testassertion.FpvSecCmMsgFifoRptrCheck_A	2147483647	80	0	0
g_testassertion.FpvSecCmMsgFifoWptrCheck_A	2147483647	80	0	0
g_testassertion.FpvSecCmPackerCountCheck_A	2147483647	80	0	0
u_state_regs_A	2147483647	2147483647	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	22278	22200	0	0
T2	380372	380288	0	0
T3	212276	212196	0	0
T7	20475	20383	0	0
T8	546477	546414	0	0
T9	23516	23356	0	0
T22	377395	377326	0	0
T23	201730	201723	0	0
T24	105556	105551	0	0
T25	357204	357139	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1242986	0	0
T1	22278	28	0	0
T2	380372	26	0	0
T3	212276	2368	0	0
T7	20475	29	0	0
T8	546477	241	0	0
T9	23516	14	0	0
T22	377395	460	0	0
T23	201730	1211	0	0
T24	105556	786	0	0
T25	357204	588	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	22278	22200	0	0
T2	380372	380288	0	0
T3	212276	212196	0	0
T7	20475	20383	0	0
T8	546477	546414	0	0
T9	23516	23356	0	0
T22	377395	377326	0	0
T23	201730	201723	0	0
T24	105556	105551	0	0
T25	357204	357139	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	327444	0	0
T1	22278	9	0	0
T2	380372	0	0	0
T3	212276	406	0	0
T7	20475	8	0	0
T8	546477	57	0	0
T9	23516	5	0	0
T22	377395	140	0	0
T23	201730	365	0	0
T24	105556	237	0	0
T25	357204	116	0	0
T26	0	12	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	706	0	0
T11	3812	0	0	0
T30	207146	0	0	0
T31	245441	0	0	0
T32	79063	0	0	0
T44	93717	17	0	0
T45	0	15	0	0
T49	0	4	0	0
T69	0	6	0	0
T70	0	8	0	0
T82	660430	0	0	0
T83	709916	0	0	0
T103	0	2	0	0
T104	0	2	0	0
T105	0	3	0	0
T106	0	2	0	0
T107	0	18	0	0
T108	206588	0	0	0
T109	151775	0	0	0
T110	38077	0	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	22278	22200	0	0
T2	380372	380288	0	0
T3	212276	212196	0	0
T7	20475	20383	0	0
T8	546477	546414	0	0
T9	23516	23356	0	0
T22	377395	377326	0	0
T23	201730	201723	0	0
T24	105556	105551	0	0
T25	357204	357139	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	885667	20	0	0
T5	0	20	0	0
T6	0	20	0	0
T111	0	10	0	0
T112	0	10	0	0
T113	136832	0	0	0
T114	31303	0	0	0
T115	438796	0	0	0
T116	155200	0	0	0
T117	256818	0	0	0
T118	975317	0	0	0
T119	105447	0	0	0
T120	777134	0	0	0
T121	225414	0	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	885667	20	0	0
T5	0	20	0	0
T6	0	20	0	0
T111	0	10	0	0
T112	0	10	0	0
T113	136832	0	0	0
T114	31303	0	0	0
T115	438796	0	0	0
T116	155200	0	0	0
T117	256818	0	0	0
T118	975317	0	0	0
T119	105447	0	0	0
T120	777134	0	0	0
T121	225414	0	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	885667	20	0	0
T5	0	20	0	0
T6	0	20	0	0
T111	0	10	0	0
T112	0	10	0	0
T113	136832	0	0	0
T114	31303	0	0	0
T115	438796	0	0	0
T116	155200	0	0	0
T117	256818	0	0	0
T118	975317	0	0	0
T119	105447	0	0	0
T120	777134	0	0	0
T121	225414	0	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	885667	20	0	0
T5	0	20	0	0
T6	0	20	0	0
T111	0	10	0	0
T112	0	10	0	0
T113	136832	0	0	0
T114	31303	0	0	0
T115	438796	0	0	0
T116	155200	0	0	0
T117	256818	0	0	0
T118	975317	0	0	0
T119	105447	0	0	0
T120	777134	0	0	0
T121	225414	0	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	885667	20	0	0
T5	0	20	0	0
T6	0	20	0	0
T111	0	10	0	0
T112	0	10	0	0
T113	136832	0	0	0
T114	31303	0	0	0
T115	438796	0	0	0
T116	155200	0	0	0
T117	256818	0	0	0
T118	975317	0	0	0
T119	105447	0	0	0
T120	777134	0	0	0
T121	225414	0	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	885667	20	0	0
T5	0	20	0	0
T6	0	20	0	0
T111	0	10	0	0
T112	0	10	0	0
T113	136832	0	0	0
T114	31303	0	0	0
T115	438796	0	0	0
T116	155200	0	0	0
T117	256818	0	0	0
T118	975317	0	0	0
T119	105447	0	0	0
T120	777134	0	0	0
T121	225414	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	885667	20	0	0
T5	0	20	0	0
T6	0	20	0	0
T111	0	10	0	0
T112	0	10	0	0
T113	136832	0	0	0
T114	31303	0	0	0
T115	438796	0	0	0
T116	155200	0	0	0
T117	256818	0	0	0
T118	975317	0	0	0
T119	105447	0	0	0
T120	777134	0	0	0
T121	225414	0	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	885667	20	0	0
T5	0	20	0	0
T6	0	20	0	0
T111	0	10	0	0
T112	0	10	0	0
T113	136832	0	0	0
T114	31303	0	0	0
T115	438796	0	0	0
T116	155200	0	0	0
T117	256818	0	0	0
T118	975317	0	0	0
T119	105447	0	0	0
T120	777134	0	0	0
T121	225414	0	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	885667	20	0	0
T5	0	20	0	0
T6	0	20	0	0
T111	0	10	0	0
T112	0	10	0	0
T113	136832	0	0	0
T114	31303	0	0	0
T115	438796	0	0	0
T116	155200	0	0	0
T117	256818	0	0	0
T118	975317	0	0	0
T119	105447	0	0	0
T120	777134	0	0	0
T121	225414	0	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	885667	20	0	0
T5	0	20	0	0
T6	0	20	0	0
T111	0	10	0	0
T112	0	10	0	0
T113	136832	0	0	0
T114	31303	0	0	0
T115	438796	0	0	0
T116	155200	0	0	0
T117	256818	0	0	0
T118	975317	0	0	0
T119	105447	0	0	0
T120	777134	0	0	0
T121	225414	0	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	885667	20	0	0
T5	0	20	0	0
T6	0	20	0	0
T111	0	10	0	0
T112	0	10	0	0
T113	136832	0	0	0
T114	31303	0	0	0
T115	438796	0	0	0
T116	155200	0	0	0
T117	256818	0	0	0
T118	975317	0	0	0
T119	105447	0	0	0
T120	777134	0	0	0
T121	225414	0	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	22278	22200	0	0
T2	380372	380288	0	0
T3	212276	212196	0	0
T7	20475	20383	0	0
T8	546477	546414	0	0
T9	23516	23356	0	0
T22	377395	377326	0	0
T23	201730	201723	0	0
T24	105556	105551	0	0
T25	357204	357139	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	22278	22200	0	0
T2	380372	380288	0	0
T3	212276	212196	0	0
T7	20475	20383	0	0
T8	546477	546414	0	0
T9	23516	23356	0	0
T22	377395	377326	0	0
T23	201730	201723	0	0
T24	105556	105551	0	0
T25	357204	357139	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	22278	22200	0	0
T2	380372	380288	0	0
T3	212276	212196	0	0
T7	20475	20383	0	0
T8	546477	546414	0	0
T9	23516	23356	0	0
T22	377395	377326	0	0
T23	201730	201723	0	0
T24	105556	105551	0	0
T25	357204	357139	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	22278	22200	0	0
T2	380372	380288	0	0
T3	212276	212196	0	0
T7	20475	20383	0	0
T8	546477	546414	0	0
T9	23516	23356	0	0
T22	377395	377326	0	0
T23	201730	201723	0	0
T24	105556	105551	0	0
T25	357204	357139	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	336043	0	0
T1	22278	9	0	0
T2	380372	64	0	0
T3	212276	413	0	0
T7	20475	9	0	0
T8	546477	58	0	0
T9	23516	4	0	0
T22	377395	143	0	0
T23	201730	374	0	0
T24	105556	246	0	0
T25	357204	116	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	22278	22200	0	0
T2	380372	380288	0	0
T3	212276	212196	0	0
T7	20475	20383	0	0
T8	546477	546414	0	0
T9	23516	23356	0	0
T22	377395	377326	0	0
T23	201730	201723	0	0
T24	105556	105551	0	0
T25	357204	357139	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	22278	22200	0	0
T2	380372	380288	0	0
T3	212276	212196	0	0
T7	20475	20383	0	0
T8	546477	546414	0	0
T9	23516	23356	0	0
T22	377395	377326	0	0
T23	201730	201723	0	0
T24	105556	105551	0	0
T25	357204	357139	0	0

g_testassertion.FpvSecCmEntropyFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	885667	20	0	0
T5	0	20	0	0
T6	0	20	0	0
T111	0	10	0	0
T112	0	10	0	0
T113	136832	0	0	0
T114	31303	0	0	0
T115	438796	0	0	0
T116	155200	0	0	0
T117	256818	0	0	0
T118	975317	0	0	0
T119	105447	0	0	0
T120	777134	0	0	0
T121	225414	0	0	0

g_testassertion.FpvSecCmHashCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	885667	20	0	0
T5	0	20	0	0
T6	0	20	0	0
T111	0	10	0	0
T112	0	10	0	0
T113	136832	0	0	0
T114	31303	0	0	0
T115	438796	0	0	0
T116	155200	0	0	0
T117	256818	0	0	0
T118	975317	0	0	0
T119	105447	0	0	0
T120	777134	0	0	0
T121	225414	0	0	0

g_testassertion.FpvSecCmMsgFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	885667	20	0	0
T5	0	20	0	0
T6	0	20	0	0
T111	0	10	0	0
T112	0	10	0	0
T113	136832	0	0	0
T114	31303	0	0	0
T115	438796	0	0	0
T116	155200	0	0	0
T117	256818	0	0	0
T118	975317	0	0	0
T119	105447	0	0	0
T120	777134	0	0	0
T121	225414	0	0	0

g_testassertion.FpvSecCmMsgFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	885667	20	0	0
T5	0	20	0	0
T6	0	20	0	0
T111	0	10	0	0
T112	0	10	0	0
T113	136832	0	0	0
T114	31303	0	0	0
T115	438796	0	0	0
T116	155200	0	0	0
T117	256818	0	0	0
T118	975317	0	0	0
T119	105447	0	0	0
T120	777134	0	0	0
T121	225414	0	0	0

g_testassertion.FpvSecCmPackerCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	885667	20	0	0
T5	0	20	0	0
T6	0	20	0	0
T111	0	10	0	0
T112	0	10	0	0
T113	136832	0	0	0
T114	31303	0	0	0
T115	438796	0	0	0
T116	155200	0	0	0
T117	256818	0	0	0
T118	975317	0	0	0
T119	105447	0	0	0
T120	777134	0	0	0
T121	225414	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	22278	22200	0	0
T2	380372	380288	0	0
T3	212276	212196	0	0
T7	20475	20383	0	0
T8	546477	546414	0	0
T9	23516	23356	0	0
T22	377395	377326	0	0
T23	201730	201723	0	0
T24	105556	105551	0	0
T25	357204	357139	0	0