Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.55	98.71	96.05	100.00	100.00	96.55	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	495751	0	0
entropy_period_rd_A	2147483647	1653	0	0
intr_enable_rd_A	2147483647	2607	0	0
prefix_0_rd_A	2147483647	1974	0	0
prefix_10_rd_A	2147483647	1966	0	0
prefix_1_rd_A	2147483647	2157	0	0
prefix_2_rd_A	2147483647	1943	0	0
prefix_3_rd_A	2147483647	2046	0	0
prefix_4_rd_A	2147483647	2048	0	0
prefix_5_rd_A	2147483647	2170	0	0
prefix_6_rd_A	2147483647	1852	0	0
prefix_7_rd_A	2147483647	1957	0	0
prefix_8_rd_A	2147483647	2042	0	0
prefix_9_rd_A	2147483647	1902	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	495751	0	0
T13	384748	39938	0	0
T20	0	41005	0	0
T21	0	29811	0	0
T128	0	30652	0	0
T129	0	24735	0	0
T130	0	98890	0	0
T131	0	32371	0	0
T132	0	53402	0	0
T133	0	43185	0	0
T134	0	42170	0	0
T135	996211	0	0	0
T136	945005	0	0	0
T137	478370	0	0	0
T138	14635	0	0	0
T139	662367	0	0	0
T140	156238	0	0	0
T141	650155	0	0	0
T142	427014	0	0	0
T143	220511	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1653	0	0
T123	0	43	0	0
T124	0	23	0	0
T129	286237	94	0	0
T134	0	154	0	0
T153	0	12	0	0
T154	0	24	0	0
T155	0	64	0	0
T156	0	28	0	0
T157	0	9	0	0
T158	0	6	0	0
T159	153687	0	0	0
T160	932465	0	0	0
T161	186177	0	0	0
T162	33953	0	0	0
T163	222645	0	0	0
T164	1716	0	0	0
T165	303355	0	0	0
T166	65714	0	0	0
T167	1726	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2607	0	0
T123	0	80	0	0
T124	0	44	0	0
T127	0	10	0	0
T129	286237	76	0	0
T134	0	127	0	0
T153	0	34	0	0
T154	0	51	0	0
T155	0	56	0	0
T159	153687	0	0	0
T160	932465	0	0	0
T161	186177	0	0	0
T162	33953	0	0	0
T163	222645	0	0	0
T164	1716	0	0	0
T165	303355	0	0	0
T166	65714	0	0	0
T167	1726	0	0	0
T168	0	17	0	0
T169	0	16	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1974	0	0
T123	0	49	0	0
T124	0	28	0	0
T129	286237	54	0	0
T134	0	78	0	0
T153	0	4	0	0
T154	0	13	0	0
T155	0	78	0	0
T156	0	39	0	0
T157	0	2	0	0
T158	0	15	0	0
T159	153687	0	0	0
T160	932465	0	0	0
T161	186177	0	0	0
T162	33953	0	0	0
T163	222645	0	0	0
T164	1716	0	0	0
T165	303355	0	0	0
T166	65714	0	0	0
T167	1726	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1966	0	0
T123	0	41	0	0
T124	0	11	0	0
T129	286237	82	0	0
T134	0	118	0	0
T153	0	68	0	0
T154	0	30	0	0
T155	0	35	0	0
T156	0	43	0	0
T157	0	5	0	0
T158	0	6	0	0
T159	153687	0	0	0
T160	932465	0	0	0
T161	186177	0	0	0
T162	33953	0	0	0
T163	222645	0	0	0
T164	1716	0	0	0
T165	303355	0	0	0
T166	65714	0	0	0
T167	1726	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2157	0	0
T123	0	36	0	0
T124	0	27	0	0
T129	286237	62	0	0
T134	0	159	0	0
T154	0	31	0	0
T155	0	40	0	0
T156	0	23	0	0
T157	0	5	0	0
T158	0	8	0	0
T159	153687	0	0	0
T160	932465	0	0	0
T161	186177	0	0	0
T162	33953	0	0	0
T163	222645	0	0	0
T164	1716	0	0	0
T165	303355	0	0	0
T166	65714	0	0	0
T167	1726	0	0	0
T170	0	22	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1943	0	0
T123	0	41	0	0
T124	0	33	0	0
T129	286237	74	0	0
T134	0	110	0	0
T154	0	31	0	0
T155	0	29	0	0
T156	0	12	0	0
T157	0	12	0	0
T158	0	9	0	0
T159	153687	0	0	0
T160	932465	0	0	0
T161	186177	0	0	0
T162	33953	0	0	0
T163	222645	0	0	0
T164	1716	0	0	0
T165	303355	0	0	0
T166	65714	0	0	0
T167	1726	0	0	0
T170	0	25	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2046	0	0
T123	0	30	0	0
T124	0	20	0	0
T129	286237	92	0	0
T134	0	166	0	0
T153	0	34	0	0
T154	0	7	0	0
T155	0	51	0	0
T156	0	27	0	0
T157	0	8	0	0
T158	0	15	0	0
T159	153687	0	0	0
T160	932465	0	0	0
T161	186177	0	0	0
T162	33953	0	0	0
T163	222645	0	0	0
T164	1716	0	0	0
T165	303355	0	0	0
T166	65714	0	0	0
T167	1726	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2048	0	0
T123	0	51	0	0
T124	0	29	0	0
T129	286237	108	0	0
T134	0	118	0	0
T153	0	32	0	0
T154	0	38	0	0
T155	0	33	0	0
T156	0	10	0	0
T157	0	5	0	0
T158	0	5	0	0
T159	153687	0	0	0
T160	932465	0	0	0
T161	186177	0	0	0
T162	33953	0	0	0
T163	222645	0	0	0
T164	1716	0	0	0
T165	303355	0	0	0
T166	65714	0	0	0
T167	1726	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2170	0	0
T123	0	54	0	0
T124	0	13	0	0
T129	286237	103	0	0
T134	0	133	0	0
T153	0	16	0	0
T154	0	14	0	0
T155	0	33	0	0
T156	0	6	0	0
T157	0	13	0	0
T158	0	6	0	0
T159	153687	0	0	0
T160	932465	0	0	0
T161	186177	0	0	0
T162	33953	0	0	0
T163	222645	0	0	0
T164	1716	0	0	0
T165	303355	0	0	0
T166	65714	0	0	0
T167	1726	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1852	0	0
T123	0	45	0	0
T124	0	18	0	0
T129	286237	57	0	0
T134	0	101	0	0
T153	0	26	0	0
T154	0	13	0	0
T155	0	40	0	0
T156	0	7	0	0
T157	0	2	0	0
T158	0	10	0	0
T159	153687	0	0	0
T160	932465	0	0	0
T161	186177	0	0	0
T162	33953	0	0	0
T163	222645	0	0	0
T164	1716	0	0	0
T165	303355	0	0	0
T166	65714	0	0	0
T167	1726	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1957	0	0
T123	0	39	0	0
T124	0	20	0	0
T129	286237	94	0	0
T134	0	128	0	0
T153	0	19	0	0
T154	0	28	0	0
T155	0	46	0	0
T156	0	17	0	0
T157	0	15	0	0
T158	0	9	0	0
T159	153687	0	0	0
T160	932465	0	0	0
T161	186177	0	0	0
T162	33953	0	0	0
T163	222645	0	0	0
T164	1716	0	0	0
T165	303355	0	0	0
T166	65714	0	0	0
T167	1726	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2042	0	0
T123	0	40	0	0
T124	0	25	0	0
T129	286237	81	0	0
T134	0	73	0	0
T153	0	12	0	0
T154	0	24	0	0
T155	0	38	0	0
T156	0	37	0	0
T157	0	2	0	0
T158	0	9	0	0
T159	153687	0	0	0
T160	932465	0	0	0
T161	186177	0	0	0
T162	33953	0	0	0
T163	222645	0	0	0
T164	1716	0	0	0
T165	303355	0	0	0
T166	65714	0	0	0
T167	1726	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1902	0	0
T123	0	41	0	0
T124	0	36	0	0
T129	286237	82	0	0
T134	0	123	0	0
T153	0	21	0	0
T154	0	13	0	0
T155	0	39	0	0
T156	0	28	0	0
T157	0	10	0	0
T158	0	8	0	0
T159	153687	0	0	0
T160	932465	0	0	0
T161	186177	0	0	0
T162	33953	0	0	0
T163	222645	0	0	0
T164	1716	0	0	0
T165	303355	0	0	0
T166	65714	0	0	0
T167	1726	0	0	0