Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	60847	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

126981

1

T1

35

T2

1

T3

84

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	103245	1			T1	84		T2	1		T3	63
values[0x0]	39752	1			T1	6		T3	29		T4	51
values[0x1]	44831	1			T1	6		T3	27		T4	63

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44061	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

143767

1

T1

47

T2

1

T3

96

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	699	1			T6	5		T7	11		T8	8
valid_sources[0x01]	617	1			T6	2		T7	9		T8	19
valid_sources[0x02]	690	1			T3	3		T5	22		T6	7
valid_sources[0x03]	956	1			T6	2		T7	6		T8	3
valid_sources[0x04]	946	1			T6	2		T7	15		T8	21
valid_sources[0x05]	614	1			T6	8		T11	2		T7	9
valid_sources[0x06]	613	1			T5	17		T6	6		T7	7
valid_sources[0x07]	1134	1			T6	4		T7	8		T8	2
valid_sources[0x08]	655	1			T6	4		T11	1		T7	9
valid_sources[0x09]	838	1			T6	3		T7	6		T8	2
valid_sources[0x0a]	771	1			T6	8		T7	10		T8	8
valid_sources[0x0b]	688	1			T4	6		T6	6		T7	12
valid_sources[0x0c]	604	1			T5	36		T6	6		T7	8
valid_sources[0x0d]	1018	1			T4	16		T5	3		T6	2
valid_sources[0x0e]	938	1			T3	4		T4	14		T6	7
valid_sources[0x0f]	1111	1			T5	59		T6	5		T7	9
valid_sources[0x10]	741	1			T3	10		T4	1		T5	2
valid_sources[0x11]	686	1			T6	3		T7	8		T32	1
valid_sources[0x12]	618	1			T3	3		T6	5		T7	9
valid_sources[0x13]	882	1			T6	2		T7	6		T8	7
valid_sources[0x14]	931	1			T6	1		T11	1		T7	8
valid_sources[0x15]	695	1			T5	3		T6	1		T7	9
valid_sources[0x16]	603	1			T6	3		T7	15		T8	11
valid_sources[0x17]	820	1			T6	1		T7	8		T8	1
valid_sources[0x18]	516	1			T6	2		T11	1		T7	8
valid_sources[0x19]	782	1			T6	5		T7	9		T8	9
valid_sources[0x1a]	665	1			T5	3		T6	6		T7	17
valid_sources[0x1b]	921	1			T5	42		T6	2		T7	7
valid_sources[0x1c]	924	1			T6	6		T7	9		T8	2
valid_sources[0x1d]	646	1			T5	17		T6	7		T7	15
valid_sources[0x1e]	725	1			T6	5		T11	1		T7	14
valid_sources[0x1f]	651	1			T6	1		T7	8		T8	8
valid_sources[0x20]	604	1			T6	3		T7	9		T8	5
valid_sources[0x21]	1106	1			T6	5		T7	8		T8	3
valid_sources[0x22]	965	1			T6	2		T7	12		T8	22
valid_sources[0x23]	761	1			T5	3		T6	5		T7	4
valid_sources[0x24]	644	1			T5	38		T6	4		T7	12
valid_sources[0x25]	821	1			T6	6		T7	9		T38	1
valid_sources[0x26]	788	1			T6	3		T7	9		T8	6
valid_sources[0x27]	735	1			T5	22		T6	8		T7	6
valid_sources[0x28]	719	1			T6	3		T7	8		T8	11
valid_sources[0x29]	655	1			T3	1		T6	7		T11	1
valid_sources[0x2a]	513	1			T6	4		T7	12		T34	2
valid_sources[0x2b]	674	1			T6	5		T7	10		T8	10
valid_sources[0x2c]	735	1			T6	2		T11	1		T7	8
valid_sources[0x2d]	764	1			T6	5		T7	6		T8	4
valid_sources[0x2e]	917	1			T6	5		T11	1		T7	12
valid_sources[0x2f]	616	1			T6	10		T7	7		T8	4
valid_sources[0x30]	765	1			T6	4		T7	11		T34	2
valid_sources[0x31]	722	1			T6	8		T7	19		T8	1
valid_sources[0x32]	722	1			T6	1		T7	11		T8	9
valid_sources[0x33]	817	1			T6	7		T7	10		T8	5
valid_sources[0x34]	592	1			T4	3		T6	3		T7	10
valid_sources[0x35]	624	1			T6	6		T7	10		T8	8
valid_sources[0x36]	1135	1			T3	6		T6	3		T7	8
valid_sources[0x37]	802	1			T6	7		T7	4		T8	3
valid_sources[0x38]	831	1			T6	7		T7	4		T8	78
valid_sources[0x39]	1085	1			T5	20		T6	4		T7	8
valid_sources[0x3a]	623	1			T4	5		T6	1		T7	7
valid_sources[0x3b]	974	1			T5	20		T6	6		T7	13
valid_sources[0x3c]	786	1			T6	6		T7	9		T8	35
valid_sources[0x3d]	683	1			T3	1		T6	6		T7	8
valid_sources[0x3e]	584	1			T1	61		T4	5		T6	4
valid_sources[0x3f]	701	1			T3	4		T6	4		T7	11
valid_sources[0x40]	599	1			T4	6		T5	13		T6	3
valid_sources[0x41]	661	1			T4	4		T6	2		T7	16
valid_sources[0x42]	536	1			T6	2		T7	5		T8	6
valid_sources[0x43]	979	1			T3	2		T6	1		T7	9
valid_sources[0x44]	767	1			T4	5		T6	3		T7	12
valid_sources[0x45]	710	1			T3	4		T6	5		T7	10
valid_sources[0x46]	688	1			T4	2		T6	4		T7	12
valid_sources[0x47]	627	1			T4	1		T6	2		T11	2
valid_sources[0x48]	682	1			T6	4		T11	2		T7	11
valid_sources[0x49]	817	1			T6	3		T7	8		T8	2
valid_sources[0x4a]	707	1			T3	3		T6	2		T7	11
valid_sources[0x4b]	753	1			T6	5		T7	5		T8	3
valid_sources[0x4c]	979	1			T6	4		T11	1		T7	10
valid_sources[0x4d]	656	1			T4	5		T6	9		T7	8
valid_sources[0x4e]	978	1			T3	3		T4	4		T6	6
valid_sources[0x4f]	599	1			T3	4		T4	8		T7	10
valid_sources[0x50]	560	1			T6	3		T7	9		T8	10
valid_sources[0x51]	656	1			T3	1		T7	2		T34	3
valid_sources[0x52]	647	1			T4	1		T6	5		T7	11
valid_sources[0x53]	721	1			T6	8		T7	14		T34	8
valid_sources[0x54]	732	1			T4	2		T6	2		T7	7
valid_sources[0x55]	632	1			T6	3		T11	1		T7	17
valid_sources[0x56]	689	1			T4	1		T6	6		T7	4
valid_sources[0x57]	624	1			T6	9		T7	6		T8	1
valid_sources[0x58]	805	1			T6	4		T7	8		T8	9
valid_sources[0x59]	488	1			T6	8		T7	11		T8	2
valid_sources[0x5a]	776	1			T4	1		T5	16		T6	5
valid_sources[0x5b]	709	1			T6	3		T7	10		T32	5
valid_sources[0x5c]	768	1			T6	6		T7	11		T34	2
valid_sources[0x5d]	1072	1			T6	3		T7	13		T8	39
valid_sources[0x5e]	881	1			T6	4		T7	4		T8	38
valid_sources[0x5f]	832	1			T6	6		T7	4		T8	10
valid_sources[0x60]	844	1			T6	9		T7	8		T8	15
valid_sources[0x61]	533	1			T3	2		T6	4		T7	11
valid_sources[0x62]	730	1			T5	40		T6	4		T11	1
valid_sources[0x63]	749	1			T6	3		T7	15		T8	5
valid_sources[0x64]	792	1			T6	5		T7	6		T8	10
valid_sources[0x65]	1082	1			T6	2		T7	8		T38	4
valid_sources[0x66]	535	1			T3	5		T6	6		T7	5
valid_sources[0x67]	692	1			T4	2		T6	3		T7	12
valid_sources[0x68]	594	1			T6	7		T7	8		T8	1
valid_sources[0x69]	689	1			T4	1		T6	8		T7	11
valid_sources[0x6a]	609	1			T4	4		T6	5		T7	11
valid_sources[0x6b]	1203	1			T4	6		T5	26		T6	6
valid_sources[0x6c]	578	1			T6	7		T7	12		T8	1
valid_sources[0x6d]	662	1			T4	10		T6	3		T11	1
valid_sources[0x6e]	547	1			T6	4		T7	10		T8	1
valid_sources[0x6f]	708	1			T6	3		T7	12		T8	6
valid_sources[0x70]	799	1			T6	4		T7	12		T8	7
valid_sources[0x71]	700	1			T3	2		T4	6		T6	1
valid_sources[0x72]	601	1			T6	4		T7	7		T8	15
valid_sources[0x73]	603	1			T3	2		T6	6		T11	1
valid_sources[0x74]	592	1			T6	3		T7	12		T8	14
valid_sources[0x75]	713	1			T5	5		T6	3		T7	4
valid_sources[0x76]	734	1			T4	4		T6	2		T7	7
valid_sources[0x77]	684	1			T6	3		T7	7		T34	7
valid_sources[0x78]	1018	1			T4	10		T6	4		T7	11
valid_sources[0x79]	623	1			T6	4		T7	6		T8	5
valid_sources[0x7a]	662	1			T3	2		T4	2		T6	8
valid_sources[0x7b]	578	1			T6	6		T7	13		T8	10
valid_sources[0x7c]	645	1			T6	7		T7	11		T8	15
valid_sources[0x7d]	805	1			T6	3		T7	13		T8	43
valid_sources[0x7e]	614	1			T6	2		T7	10		T32	50
valid_sources[0x7f]	791	1			T3	2		T6	1		T7	14
valid_sources[0x80]	798	1			T6	2		T7	10		T8	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

57555

1

T1

32

T2

1

T3

34

values[0x0]

all_enables

biggest_size

34881

1

T1

2

T3

26

T4

48

values[0x1]

all_enables

biggest_size

34545

1

T1

1

T3

24

T4

57