Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

74778

1

T1

61

T3

35

T4

70

full_word

127845

1

T1

35

T2

1

T3

84

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	202313	1			T1	96		T2	1		T3	119
auto[TlIntgErrCmd]	93	1			T7	10		T8	6		T26	3
auto[TlIntgErrData]	103	1			T7	6		T8	6		T26	2
auto[TlIntgErrBoth]	114	1			T7	4		T8	8		T26	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105770

1

T1

84

T2

1

T3

63

auto[1]

96853

1

T1

12

T3

56

T4

114

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	47887	1			T1	52		T3	29		T4	61
auto[TlIntgErrNone]	partial	auto[1]	26606	1			T1	9		T3	6		T4	9
auto[TlIntgErrNone]	full_word	auto[0]	57743	1			T1	32		T2	1		T3	34
auto[TlIntgErrNone]	full_word	auto[1]	70077	1			T1	3		T3	50		T4	105
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T7	4		T26	2		T33	2
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T7	5		T8	6		T26	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T7	1		T71	1		T74	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T65	1		T75	1		T74	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T7	2		T8	3		T26	1
auto[TlIntgErrData]	partial	auto[1]	41	1			T7	3		T8	3		T33	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T7	1		T26	1		T71	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T75	1		T76	1		T73	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T8	1		T26	2		T33	2
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T7	4		T8	4		T26	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T77	1		T73	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T8	3		T65	1		T78	1