Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 22 | 0 | 0.00 |
| ALWAYS | 70 | 4 | 0 | 0.00 |
| CONT_ASSIGN | 84 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 85 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 86 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 87 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 88 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 92 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 93 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 98 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 99 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 100 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 145 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 146 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 154 | 1 | 0 | 0.00 |
| ALWAYS | 157 | 2 | 0 | 0.00 |
| CONT_ASSIGN | 175 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 176 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 180 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 70 |
0 |
1 |
| 71 |
0 |
1 |
| 72 |
0 |
1 |
| 73 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
| 84 |
0 |
1 |
| 85 |
0 |
1 |
| 86 |
0 |
1 |
| 87 |
0 |
1 |
| 88 |
0 |
1 |
| 92 |
0 |
1 |
| 93 |
0 |
1 |
| 98 |
0 |
1 |
| 99 |
0 |
1 |
| 100 |
0 |
1 |
| 145 |
0 |
1 |
| 146 |
0 |
1 |
| 154 |
0 |
1 |
| 157 |
0 |
1 |
| 158 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
| 175 |
0 |
1 |
| 176 |
0 |
1 |
| 180 |
0 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo
| Total | Covered | Percent |
|---|
| Conditions | 26 | 0 | 0.00 |
| Logical | 26 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
10 |
0 |
0.00 |
| TERNARY |
88 |
3 |
0 |
0.00 |
| TERNARY |
180 |
2 |
0 |
0.00 |
| IF |
70 |
3 |
0 |
0.00 |
| IF |
157 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 157 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 21 | 0 | 0.00 |
| ALWAYS | 70 | 4 | 0 | 0.00 |
| CONT_ASSIGN | 84 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 85 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 86 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 87 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 88 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 92 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 93 | 0 | 0 | |
| CONT_ASSIGN | 98 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 99 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 100 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 145 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 146 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 154 | 1 | 0 | 0.00 |
| ALWAYS | 157 | 2 | 0 | 0.00 |
| CONT_ASSIGN | 175 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 176 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 180 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 70 |
0 |
1 |
| 71 |
0 |
1 |
| 72 |
0 |
1 |
| 73 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
| 84 |
0 |
1 |
| 85 |
0 |
1 |
| 86 |
0 |
1 |
| 87 |
0 |
1 |
| 88 |
0 |
1 |
| 92 |
0 |
1 |
| 93 |
|
unreachable |
| 98 |
0 |
1 |
| 99 |
0 |
1 |
| 100 |
0 |
1 |
| 145 |
0 |
1 |
| 146 |
0 |
1 |
| 154 |
0 |
1 |
| 157 |
0 |
1 |
| 158 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
| 175 |
0 |
1 |
| 176 |
0 |
1 |
| 180 |
0 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo
| Total | Covered | Percent |
|---|
| Conditions | 23 | 0 | 0.00 |
| Logical | 23 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Unreachable | |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
10 |
0 |
0.00 |
| TERNARY |
88 |
3 |
0 |
0.00 |
| TERNARY |
180 |
2 |
0 |
0.00 |
| IF |
70 |
3 |
0 |
0.00 |
| IF |
157 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 157 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 20 | 0 | 0.00 |
| ALWAYS | 70 | 4 | 0 | 0.00 |
| CONT_ASSIGN | 84 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 85 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 86 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 87 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 88 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 92 | 0 | 0 | |
| CONT_ASSIGN | 93 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 98 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 99 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 100 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 145 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 146 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 154 | 1 | 0 | 0.00 |
| ALWAYS | 157 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 172 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 173 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 180 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 70 |
0 |
1 |
| 71 |
0 |
1 |
| 72 |
0 |
1 |
| 73 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
| 84 |
0 |
1 |
| 85 |
0 |
1 |
| 86 |
0 |
1 |
| 87 |
0 |
1 |
| 88 |
0 |
1 |
| 92 |
|
unreachable |
| 93 |
0 |
1 |
| 98 |
0 |
1 |
| 99 |
0 |
1 |
| 100 |
0 |
1 |
| 145 |
0 |
1 |
| 146 |
0 |
1 |
| 154 |
0 |
1 |
| 157 |
0 |
1 |
| 158 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
| 172 |
0 |
1 |
| 173 |
0 |
1 |
| 180 |
0 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo
| Total | Covered | Percent |
|---|
| Conditions | 27 | 0 | 0.00 |
| Logical | 27 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 172
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Unreachable | |
LINE 172
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Unreachable | |
LINE 173
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Unreachable | |
| 1 | 1 | Not Covered | |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
10 |
0 |
0.00 |
| TERNARY |
88 |
3 |
0 |
0.00 |
| TERNARY |
172 |
1 |
0 |
0.00 |
| TERNARY |
180 |
2 |
0 |
0.00 |
| IF |
70 |
3 |
0 |
0.00 |
| IF |
157 |
1 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 172 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Unreachable |
|
| 0 |
Not Covered |
|
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 157 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
| -1- | Status | Tests |
| 1 |
Unreachable |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 22 | 0 | 0.00 |
| ALWAYS | 70 | 4 | 0 | 0.00 |
| CONT_ASSIGN | 84 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 85 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 86 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 87 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 88 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 92 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 93 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 98 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 99 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 100 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 145 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 146 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 162 | 1 | 0 | 0.00 |
| ALWAYS | 165 | 2 | 0 | 0.00 |
| CONT_ASSIGN | 172 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 173 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 180 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 70 |
0 |
1 |
| 71 |
0 |
1 |
| 72 |
0 |
1 |
| 73 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
| 84 |
0 |
1 |
| 85 |
0 |
1 |
| 86 |
0 |
1 |
| 87 |
0 |
1 |
| 88 |
0 |
1 |
| 92 |
0 |
1 |
| 93 |
0 |
1 |
| 98 |
0 |
1 |
| 99 |
0 |
1 |
| 100 |
0 |
1 |
| 145 |
0 |
1 |
| 146 |
0 |
1 |
| 162 |
0 |
1 |
| 165 |
0 |
1 |
| 166 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
| 172 |
0 |
1 |
| 173 |
0 |
1 |
| 180 |
0 |
1 |
Cond Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo
| Total | Covered | Percent |
|---|
| Conditions | 34 | 0 | 0.00 |
| Logical | 34 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 172
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 172
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 173
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
12 |
0 |
0.00 |
| TERNARY |
88 |
3 |
0 |
0.00 |
| TERNARY |
172 |
2 |
0 |
0.00 |
| TERNARY |
180 |
2 |
0 |
0.00 |
| IF |
70 |
3 |
0 |
0.00 |
| IF |
157 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 172 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 157 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 22 | 0 | 0.00 |
| ALWAYS | 70 | 4 | 0 | 0.00 |
| CONT_ASSIGN | 84 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 85 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 86 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 87 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 88 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 92 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 93 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 98 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 99 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 100 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 145 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 146 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 154 | 1 | 0 | 0.00 |
| ALWAYS | 157 | 2 | 0 | 0.00 |
| CONT_ASSIGN | 175 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 176 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 180 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 70 |
0 |
1 |
| 71 |
0 |
1 |
| 72 |
0 |
1 |
| 73 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
| 84 |
0 |
1 |
| 85 |
0 |
1 |
| 86 |
0 |
1 |
| 87 |
0 |
1 |
| 88 |
0 |
1 |
| 92 |
0 |
1 |
| 93 |
0 |
1 |
| 98 |
0 |
1 |
| 99 |
0 |
1 |
| 100 |
0 |
1 |
| 145 |
0 |
1 |
| 146 |
0 |
1 |
| 154 |
0 |
1 |
| 157 |
0 |
1 |
| 158 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
| 175 |
0 |
1 |
| 176 |
0 |
1 |
| 180 |
0 |
1 |
Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo
| Total | Covered | Percent |
|---|
| Conditions | 26 | 0 | 0.00 |
| Logical | 26 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
10 |
0 |
0.00 |
| TERNARY |
88 |
3 |
0 |
0.00 |
| TERNARY |
180 |
2 |
0 |
0.00 |
| IF |
70 |
3 |
0 |
0.00 |
| IF |
157 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 157 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 22 | 0 | 0.00 |
| ALWAYS | 70 | 4 | 0 | 0.00 |
| CONT_ASSIGN | 84 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 85 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 86 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 87 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 88 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 92 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 93 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 98 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 99 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 100 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 145 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 146 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 154 | 1 | 0 | 0.00 |
| ALWAYS | 157 | 2 | 0 | 0.00 |
| CONT_ASSIGN | 175 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 176 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 180 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 70 |
0 |
1 |
| 71 |
0 |
1 |
| 72 |
0 |
1 |
| 73 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
| 84 |
0 |
1 |
| 85 |
0 |
1 |
| 86 |
0 |
1 |
| 87 |
0 |
1 |
| 88 |
0 |
1 |
| 92 |
0 |
1 |
| 93 |
0 |
1 |
| 98 |
0 |
1 |
| 99 |
0 |
1 |
| 100 |
0 |
1 |
| 145 |
0 |
1 |
| 146 |
0 |
1 |
| 154 |
0 |
1 |
| 157 |
0 |
1 |
| 158 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
| 175 |
0 |
1 |
| 176 |
0 |
1 |
| 180 |
0 |
1 |
Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo
| Total | Covered | Percent |
|---|
| Conditions | 26 | 0 | 0.00 |
| Logical | 26 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
10 |
0 |
0.00 |
| TERNARY |
88 |
3 |
0 |
0.00 |
| TERNARY |
180 |
2 |
0 |
0.00 |
| IF |
70 |
3 |
0 |
0.00 |
| IF |
157 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 157 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 22 | 0 | 0.00 |
| ALWAYS | 70 | 4 | 0 | 0.00 |
| CONT_ASSIGN | 84 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 85 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 86 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 87 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 88 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 92 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 93 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 98 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 99 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 100 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 145 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 146 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 154 | 1 | 0 | 0.00 |
| ALWAYS | 157 | 2 | 0 | 0.00 |
| CONT_ASSIGN | 172 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 173 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 180 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 70 |
0 |
1 |
| 71 |
0 |
1 |
| 72 |
0 |
1 |
| 73 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
| 84 |
0 |
1 |
| 85 |
0 |
1 |
| 86 |
0 |
1 |
| 87 |
0 |
1 |
| 88 |
0 |
1 |
| 92 |
0 |
1 |
| 93 |
0 |
1 |
| 98 |
0 |
1 |
| 99 |
0 |
1 |
| 100 |
0 |
1 |
| 145 |
0 |
1 |
| 146 |
0 |
1 |
| 154 |
0 |
1 |
| 157 |
0 |
1 |
| 158 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
| 172 |
0 |
1 |
| 173 |
0 |
1 |
| 180 |
0 |
1 |
Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo
| Total | Covered | Percent |
|---|
| Conditions | 34 | 0 | 0.00 |
| Logical | 34 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 172
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 172
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 173
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
12 |
0 |
0.00 |
| TERNARY |
88 |
3 |
0 |
0.00 |
| TERNARY |
172 |
2 |
0 |
0.00 |
| TERNARY |
180 |
2 |
0 |
0.00 |
| IF |
70 |
3 |
0 |
0.00 |
| IF |
157 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 172 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 157 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 44 |
1 |
1 |
| 45 |
1 |
1 |
| 48 |
1 |
1 |
| 49 |
1 |
1 |
| 53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1555316 |
320656 |
0 |
0 |
| T1 |
1375 |
151 |
0 |
0 |
| T2 |
749 |
1 |
0 |
0 |
| T3 |
1019 |
234 |
0 |
0 |
| T4 |
1707 |
449 |
0 |
0 |
| T5 |
2764 |
1388 |
0 |
0 |
| T6 |
3162 |
2285 |
0 |
0 |
| T7 |
8580 |
4970 |
0 |
0 |
| T8 |
18178 |
4889 |
0 |
0 |
| T11 |
1194 |
38 |
0 |
0 |
| T12 |
1141 |
22 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1555316 |
1504781 |
0 |
0 |
| T1 |
1375 |
1227 |
0 |
0 |
| T2 |
749 |
689 |
0 |
0 |
| T3 |
1019 |
948 |
0 |
0 |
| T4 |
1707 |
1508 |
0 |
0 |
| T5 |
2764 |
2528 |
0 |
0 |
| T6 |
3162 |
3106 |
0 |
0 |
| T7 |
8580 |
6935 |
0 |
0 |
| T8 |
18178 |
16522 |
0 |
0 |
| T11 |
1194 |
1116 |
0 |
0 |
| T12 |
1141 |
1057 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1555316 |
1504781 |
0 |
0 |
| T1 |
1375 |
1227 |
0 |
0 |
| T2 |
749 |
689 |
0 |
0 |
| T3 |
1019 |
948 |
0 |
0 |
| T4 |
1707 |
1508 |
0 |
0 |
| T5 |
2764 |
2528 |
0 |
0 |
| T6 |
3162 |
3106 |
0 |
0 |
| T7 |
8580 |
6935 |
0 |
0 |
| T8 |
18178 |
16522 |
0 |
0 |
| T11 |
1194 |
1116 |
0 |
0 |
| T12 |
1141 |
1057 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1555316 |
1504781 |
0 |
0 |
| T1 |
1375 |
1227 |
0 |
0 |
| T2 |
749 |
689 |
0 |
0 |
| T3 |
1019 |
948 |
0 |
0 |
| T4 |
1707 |
1508 |
0 |
0 |
| T5 |
2764 |
2528 |
0 |
0 |
| T6 |
3162 |
3106 |
0 |
0 |
| T7 |
8580 |
6935 |
0 |
0 |
| T8 |
18178 |
16522 |
0 |
0 |
| T11 |
1194 |
1116 |
0 |
0 |
| T12 |
1141 |
1057 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
214 |
214 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 44 |
1 |
1 |
| 45 |
1 |
1 |
| 48 |
1 |
1 |
| 49 |
1 |
1 |
| 53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1555316 |
491632 |
0 |
0 |
| T1 |
1375 |
96 |
0 |
0 |
| T2 |
749 |
1 |
0 |
0 |
| T3 |
1019 |
119 |
0 |
0 |
| T4 |
1707 |
227 |
0 |
0 |
| T5 |
2764 |
643 |
0 |
0 |
| T6 |
3162 |
1198 |
0 |
0 |
| T7 |
8580 |
2551 |
0 |
0 |
| T8 |
18178 |
2516 |
0 |
0 |
| T11 |
1194 |
119 |
0 |
0 |
| T12 |
1141 |
22 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1555316 |
1504781 |
0 |
0 |
| T1 |
1375 |
1227 |
0 |
0 |
| T2 |
749 |
689 |
0 |
0 |
| T3 |
1019 |
948 |
0 |
0 |
| T4 |
1707 |
1508 |
0 |
0 |
| T5 |
2764 |
2528 |
0 |
0 |
| T6 |
3162 |
3106 |
0 |
0 |
| T7 |
8580 |
6935 |
0 |
0 |
| T8 |
18178 |
16522 |
0 |
0 |
| T11 |
1194 |
1116 |
0 |
0 |
| T12 |
1141 |
1057 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1555316 |
1504781 |
0 |
0 |
| T1 |
1375 |
1227 |
0 |
0 |
| T2 |
749 |
689 |
0 |
0 |
| T3 |
1019 |
948 |
0 |
0 |
| T4 |
1707 |
1508 |
0 |
0 |
| T5 |
2764 |
2528 |
0 |
0 |
| T6 |
3162 |
3106 |
0 |
0 |
| T7 |
8580 |
6935 |
0 |
0 |
| T8 |
18178 |
16522 |
0 |
0 |
| T11 |
1194 |
1116 |
0 |
0 |
| T12 |
1141 |
1057 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1555316 |
1504781 |
0 |
0 |
| T1 |
1375 |
1227 |
0 |
0 |
| T2 |
749 |
689 |
0 |
0 |
| T3 |
1019 |
948 |
0 |
0 |
| T4 |
1707 |
1508 |
0 |
0 |
| T5 |
2764 |
2528 |
0 |
0 |
| T6 |
3162 |
3106 |
0 |
0 |
| T7 |
8580 |
6935 |
0 |
0 |
| T8 |
18178 |
16522 |
0 |
0 |
| T11 |
1194 |
1116 |
0 |
0 |
| T12 |
1141 |
1057 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
214 |
214 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 44 |
1 |
1 |
| 45 |
1 |
1 |
| 48 |
1 |
1 |
| 49 |
1 |
1 |
| 53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1555316 |
5254 |
0 |
0 |
| T9 |
14531 |
753 |
0 |
0 |
| T13 |
3511 |
7 |
0 |
0 |
| T14 |
0 |
236 |
0 |
0 |
| T15 |
0 |
282 |
0 |
0 |
| T17 |
0 |
193 |
0 |
0 |
| T18 |
0 |
36 |
0 |
0 |
| T19 |
0 |
282 |
0 |
0 |
| T20 |
0 |
88 |
0 |
0 |
| T21 |
0 |
330 |
0 |
0 |
| T22 |
0 |
340 |
0 |
0 |
| T23 |
1752 |
0 |
0 |
0 |
| T24 |
1409 |
0 |
0 |
0 |
| T25 |
2900 |
0 |
0 |
0 |
| T26 |
6414 |
0 |
0 |
0 |
| T27 |
72790 |
0 |
0 |
0 |
| T28 |
951 |
0 |
0 |
0 |
| T29 |
1261 |
0 |
0 |
0 |
| T30 |
4424 |
0 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1555316 |
1504781 |
0 |
0 |
| T1 |
1375 |
1227 |
0 |
0 |
| T2 |
749 |
689 |
0 |
0 |
| T3 |
1019 |
948 |
0 |
0 |
| T4 |
1707 |
1508 |
0 |
0 |
| T5 |
2764 |
2528 |
0 |
0 |
| T6 |
3162 |
3106 |
0 |
0 |
| T7 |
8580 |
6935 |
0 |
0 |
| T8 |
18178 |
16522 |
0 |
0 |
| T11 |
1194 |
1116 |
0 |
0 |
| T12 |
1141 |
1057 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1555316 |
1504781 |
0 |
0 |
| T1 |
1375 |
1227 |
0 |
0 |
| T2 |
749 |
689 |
0 |
0 |
| T3 |
1019 |
948 |
0 |
0 |
| T4 |
1707 |
1508 |
0 |
0 |
| T5 |
2764 |
2528 |
0 |
0 |
| T6 |
3162 |
3106 |
0 |
0 |
| T7 |
8580 |
6935 |
0 |
0 |
| T8 |
18178 |
16522 |
0 |
0 |
| T11 |
1194 |
1116 |
0 |
0 |
| T12 |
1141 |
1057 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1555316 |
1504781 |
0 |
0 |
| T1 |
1375 |
1227 |
0 |
0 |
| T2 |
749 |
689 |
0 |
0 |
| T3 |
1019 |
948 |
0 |
0 |
| T4 |
1707 |
1508 |
0 |
0 |
| T5 |
2764 |
2528 |
0 |
0 |
| T6 |
3162 |
3106 |
0 |
0 |
| T7 |
8580 |
6935 |
0 |
0 |
| T8 |
18178 |
16522 |
0 |
0 |
| T11 |
1194 |
1116 |
0 |
0 |
| T12 |
1141 |
1057 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
214 |
214 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 44 |
1 |
1 |
| 45 |
1 |
1 |
| 48 |
1 |
1 |
| 49 |
1 |
1 |
| 53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1555316 |
10762 |
0 |
0 |
| T9 |
14531 |
2560 |
0 |
0 |
| T13 |
3511 |
6 |
0 |
0 |
| T14 |
0 |
207 |
0 |
0 |
| T15 |
0 |
214 |
0 |
0 |
| T17 |
0 |
191 |
0 |
0 |
| T18 |
0 |
30 |
0 |
0 |
| T19 |
0 |
209 |
0 |
0 |
| T20 |
0 |
451 |
0 |
0 |
| T21 |
0 |
322 |
0 |
0 |
| T22 |
0 |
1404 |
0 |
0 |
| T23 |
1752 |
0 |
0 |
0 |
| T24 |
1409 |
0 |
0 |
0 |
| T25 |
2900 |
0 |
0 |
0 |
| T26 |
6414 |
0 |
0 |
0 |
| T27 |
72790 |
0 |
0 |
0 |
| T28 |
951 |
0 |
0 |
0 |
| T29 |
1261 |
0 |
0 |
0 |
| T30 |
4424 |
0 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1555316 |
1504781 |
0 |
0 |
| T1 |
1375 |
1227 |
0 |
0 |
| T2 |
749 |
689 |
0 |
0 |
| T3 |
1019 |
948 |
0 |
0 |
| T4 |
1707 |
1508 |
0 |
0 |
| T5 |
2764 |
2528 |
0 |
0 |
| T6 |
3162 |
3106 |
0 |
0 |
| T7 |
8580 |
6935 |
0 |
0 |
| T8 |
18178 |
16522 |
0 |
0 |
| T11 |
1194 |
1116 |
0 |
0 |
| T12 |
1141 |
1057 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1555316 |
1504781 |
0 |
0 |
| T1 |
1375 |
1227 |
0 |
0 |
| T2 |
749 |
689 |
0 |
0 |
| T3 |
1019 |
948 |
0 |
0 |
| T4 |
1707 |
1508 |
0 |
0 |
| T5 |
2764 |
2528 |
0 |
0 |
| T6 |
3162 |
3106 |
0 |
0 |
| T7 |
8580 |
6935 |
0 |
0 |
| T8 |
18178 |
16522 |
0 |
0 |
| T11 |
1194 |
1116 |
0 |
0 |
| T12 |
1141 |
1057 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1555316 |
1504781 |
0 |
0 |
| T1 |
1375 |
1227 |
0 |
0 |
| T2 |
749 |
689 |
0 |
0 |
| T3 |
1019 |
948 |
0 |
0 |
| T4 |
1707 |
1508 |
0 |
0 |
| T5 |
2764 |
2528 |
0 |
0 |
| T6 |
3162 |
3106 |
0 |
0 |
| T7 |
8580 |
6935 |
0 |
0 |
| T8 |
18178 |
16522 |
0 |
0 |
| T11 |
1194 |
1116 |
0 |
0 |
| T12 |
1141 |
1057 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
214 |
214 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |