Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1555316	24472	0	0
DepthKnown_A	1555316	1504781	0	0
RvalidKnown_A	1555316	1504781	0	0
WreadyKnown_A	1555316	1504781	0	0
gen_passthru_fifo.paramCheckPass	214	214	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	24472	0	0
T9	14531	596	0	0
T13	3511	1261	0	0
T14	0	421	0	0
T15	0	423	0	0
T16	0	721	0	0
T17	0	480	0	0
T18	0	484	0	0
T19	0	190	0	0
T20	0	437	0	0
T23	1752	0	0	0
T24	1409	0	0	0
T25	2900	0	0	0
T26	6414	0	0	0
T27	72790	0	0	0
T28	951	0	0	0
T29	1261	0	0	0
T30	4424	0	0	0
T31	0	401	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	1504781	0	0
T1	1375	1227	0	0
T2	749	689	0	0
T3	1019	948	0	0
T4	1707	1508	0	0
T5	2764	2528	0	0
T6	3162	3106	0	0
T7	8580	6935	0	0
T8	18178	16522	0	0
T11	1194	1116	0	0
T12	1141	1057	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	1504781	0	0
T1	1375	1227	0	0
T2	749	689	0	0
T3	1019	948	0	0
T4	1707	1508	0	0
T5	2764	2528	0	0
T6	3162	3106	0	0
T7	8580	6935	0	0
T8	18178	16522	0	0
T11	1194	1116	0	0
T12	1141	1057	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	1504781	0	0
T1	1375	1227	0	0
T2	749	689	0	0
T3	1019	948	0	0
T4	1707	1508	0	0
T5	2764	2528	0	0
T6	3162	3106	0	0
T7	8580	6935	0	0
T8	18178	16522	0	0
T11	1194	1116	0	0
T12	1141	1057	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	214	214	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1555316	36395	0	0
DepthKnown_A	1555316	1504781	0	0
RvalidKnown_A	1555316	1504781	0	0
WreadyKnown_A	1555316	1504781	0	0
gen_passthru_fifo.paramCheckPass	214	214	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	36395	0	0
T9	14531	2133	0	0
T13	3511	660	0	0
T14	0	349	0	0
T15	0	313	0	0
T16	0	361	0	0
T17	0	466	0	0
T18	0	274	0	0
T19	0	151	0	0
T20	0	1340	0	0
T23	1752	0	0	0
T24	1409	0	0	0
T25	2900	0	0	0
T26	6414	0	0	0
T27	72790	0	0	0
T28	951	0	0	0
T29	1261	0	0	0
T30	4424	0	0	0
T31	0	379	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	1504781	0	0
T1	1375	1227	0	0
T2	749	689	0	0
T3	1019	948	0	0
T4	1707	1508	0	0
T5	2764	2528	0	0
T6	3162	3106	0	0
T7	8580	6935	0	0
T8	18178	16522	0	0
T11	1194	1116	0	0
T12	1141	1057	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	1504781	0	0
T1	1375	1227	0	0
T2	749	689	0	0
T3	1019	948	0	0
T4	1707	1508	0	0
T5	2764	2528	0	0
T6	3162	3106	0	0
T7	8580	6935	0	0
T8	18178	16522	0	0
T11	1194	1116	0	0
T12	1141	1057	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	1504781	0	0
T1	1375	1227	0	0
T2	749	689	0	0
T3	1019	948	0	0
T4	1707	1508	0	0
T5	2764	2528	0	0
T6	3162	3106	0	0
T7	8580	6935	0	0
T8	18178	16522	0	0
T11	1194	1116	0	0
T12	1141	1057	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	214	214	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1555316	280148	0	0
DepthKnown_A	1555316	1504781	0	0
RvalidKnown_A	1555316	1504781	0	0
WreadyKnown_A	1555316	1504781	0	0
gen_passthru_fifo.paramCheckPass	214	214	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	280148	0	0
T1	1375	151	0	0
T2	749	1	0	0
T3	1019	234	0	0
T4	1707	449	0	0
T5	2764	1388	0	0
T6	3162	2285	0	0
T7	8580	4970	0	0
T8	18178	4889	0	0
T11	1194	38	0	0
T12	1141	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	1504781	0	0
T1	1375	1227	0	0
T2	749	689	0	0
T3	1019	948	0	0
T4	1707	1508	0	0
T5	2764	2528	0	0
T6	3162	3106	0	0
T7	8580	6935	0	0
T8	18178	16522	0	0
T11	1194	1116	0	0
T12	1141	1057	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	1504781	0	0
T1	1375	1227	0	0
T2	749	689	0	0
T3	1019	948	0	0
T4	1707	1508	0	0
T5	2764	2528	0	0
T6	3162	3106	0	0
T7	8580	6935	0	0
T8	18178	16522	0	0
T11	1194	1116	0	0
T12	1141	1057	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	1504781	0	0
T1	1375	1227	0	0
T2	749	689	0	0
T3	1019	948	0	0
T4	1707	1508	0	0
T5	2764	2528	0	0
T6	3162	3106	0	0
T7	8580	6935	0	0
T8	18178	16522	0	0
T11	1194	1116	0	0
T12	1141	1057	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	214	214	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1555316	444475	0	0
DepthKnown_A	1555316	1504781	0	0
RvalidKnown_A	1555316	1504781	0	0
WreadyKnown_A	1555316	1504781	0	0
gen_passthru_fifo.paramCheckPass	214	214	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	444475	0	0
T1	1375	96	0	0
T2	749	1	0	0
T3	1019	119	0	0
T4	1707	227	0	0
T5	2764	643	0	0
T6	3162	1198	0	0
T7	8580	2551	0	0
T8	18178	2516	0	0
T11	1194	119	0	0
T12	1141	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	1504781	0	0
T1	1375	1227	0	0
T2	749	689	0	0
T3	1019	948	0	0
T4	1707	1508	0	0
T5	2764	2528	0	0
T6	3162	3106	0	0
T7	8580	6935	0	0
T8	18178	16522	0	0
T11	1194	1116	0	0
T12	1141	1057	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	1504781	0	0
T1	1375	1227	0	0
T2	749	689	0	0
T3	1019	948	0	0
T4	1707	1508	0	0
T5	2764	2528	0	0
T6	3162	3106	0	0
T7	8580	6935	0	0
T8	18178	16522	0	0
T11	1194	1116	0	0
T12	1141	1057	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	1504781	0	0
T1	1375	1227	0	0
T2	749	689	0	0
T3	1019	948	0	0
T4	1707	1508	0	0
T5	2764	2528	0	0
T6	3162	3106	0	0
T7	8580	6935	0	0
T8	18178	16522	0	0
T11	1194	1116	0	0
T12	1141	1057	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	214	214	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0