Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
1.32	0.00	0.00	6.61	0.00	0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1555316	3540	0	0
entropy_period_rd_A	1555316	2250	0	0
intr_enable_rd_A	1555316	3295	0	0
prefix_0_rd_A	1555316	2435	0	0
prefix_10_rd_A	1555316	2613	0	0
prefix_1_rd_A	1555316	2354	0	0
prefix_2_rd_A	1555316	2551	0	0
prefix_3_rd_A	1555316	2505	0	0
prefix_4_rd_A	1555316	2454	0	0
prefix_5_rd_A	1555316	2539	0	0
prefix_6_rd_A	1555316	2618	0	0
prefix_7_rd_A	1555316	2621	0	0
prefix_8_rd_A	1555316	2411	0	0
prefix_9_rd_A	1555316	2512	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	3540	0	0
T7	8580	3	0	0
T8	18178	3	0	0
T9	0	184	0	0
T12	1141	0	0	0
T13	0	3	0	0
T14	0	273	0	0
T15	0	159	0	0
T17	0	244	0	0
T18	0	22	0	0
T19	0	39	0	0
T32	9794	0	0	0
T33	0	2	0	0
T34	3216	0	0	0
T35	1681	0	0	0
T36	1319	0	0	0
T37	1928	0	0	0
T38	4667	0	0	0
T39	5967	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	2250	0	0
T13	3511	0	0	0
T14	3106	0	0	0
T15	3577	0	0	0
T25	2900	19	0	0
T26	6414	0	0	0
T27	72790	100	0	0
T28	951	0	0	0
T29	1261	0	0	0
T30	4424	0	0	0
T33	0	15	0	0
T41	3455	0	0	0
T54	0	9	0	0
T57	0	26	0	0
T63	0	10	0	0
T64	0	231	0	0
T65	0	87	0	0
T66	0	21	0	0
T67	0	241	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	3295	0	0
T7	8580	0	0	0
T8	18178	0	0	0
T11	1194	24	0	0
T12	1141	0	0	0
T25	0	11	0	0
T27	0	221	0	0
T28	0	8	0	0
T32	9794	0	0	0
T33	0	23	0	0
T34	3216	0	0	0
T35	1681	22	0	0
T36	1319	28	0	0
T37	1928	0	0	0
T38	4667	0	0	0
T48	0	22	0	0
T63	0	12	0	0
T68	0	12	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	2435	0	0
T13	3511	0	0	0
T14	3106	0	0	0
T15	3577	0	0	0
T25	2900	11	0	0
T26	6414	0	0	0
T27	72790	231	0	0
T28	951	0	0	0
T29	1261	0	0	0
T30	4424	0	0	0
T33	0	18	0	0
T41	3455	0	0	0
T54	0	26	0	0
T57	0	9	0	0
T64	0	191	0	0
T65	0	33	0	0
T66	0	36	0	0
T67	0	215	0	0
T69	0	13	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	2613	0	0
T13	3511	0	0	0
T14	3106	0	0	0
T15	3577	0	0	0
T25	2900	7	0	0
T26	6414	0	0	0
T27	72790	224	0	0
T28	951	0	0	0
T29	1261	0	0	0
T30	4424	0	0	0
T33	0	37	0	0
T41	3455	0	0	0
T54	0	17	0	0
T57	0	17	0	0
T63	0	6	0	0
T64	0	271	0	0
T65	0	39	0	0
T66	0	24	0	0
T67	0	219	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	2354	0	0
T13	3511	0	0	0
T14	3106	0	0	0
T15	3577	0	0	0
T25	2900	17	0	0
T26	6414	0	0	0
T27	72790	216	0	0
T28	951	0	0	0
T29	1261	0	0	0
T30	4424	0	0	0
T33	0	39	0	0
T41	3455	0	0	0
T54	0	39	0	0
T57	0	18	0	0
T63	0	4	0	0
T64	0	209	0	0
T65	0	32	0	0
T66	0	36	0	0
T67	0	170	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	2551	0	0
T13	3511	0	0	0
T14	3106	0	0	0
T15	3577	0	0	0
T25	2900	7	0	0
T26	6414	0	0	0
T27	72790	257	0	0
T28	951	0	0	0
T29	1261	0	0	0
T30	4424	0	0	0
T33	0	22	0	0
T41	3455	0	0	0
T54	0	25	0	0
T57	0	15	0	0
T63	0	9	0	0
T64	0	306	0	0
T65	0	38	0	0
T66	0	61	0	0
T67	0	186	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	2505	0	0
T13	3511	0	0	0
T14	3106	0	0	0
T15	3577	0	0	0
T25	2900	8	0	0
T26	6414	0	0	0
T27	72790	223	0	0
T28	951	0	0	0
T29	1261	0	0	0
T30	4424	0	0	0
T33	0	21	0	0
T41	3455	0	0	0
T54	0	17	0	0
T57	0	34	0	0
T63	0	1	0	0
T64	0	286	0	0
T65	0	39	0	0
T66	0	42	0	0
T67	0	238	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	2454	0	0
T13	3511	0	0	0
T14	3106	0	0	0
T15	3577	0	0	0
T25	2900	9	0	0
T26	6414	0	0	0
T27	72790	214	0	0
T28	951	0	0	0
T29	1261	0	0	0
T30	4424	0	0	0
T33	0	17	0	0
T41	3455	0	0	0
T54	0	58	0	0
T57	0	34	0	0
T63	0	4	0	0
T64	0	232	0	0
T65	0	27	0	0
T66	0	9	0	0
T67	0	222	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	2539	0	0
T9	14531	8	0	0
T13	3511	0	0	0
T23	1752	0	0	0
T24	1409	0	0	0
T25	2900	12	0	0
T26	6414	0	0	0
T27	72790	213	0	0
T28	951	0	0	0
T29	1261	0	0	0
T30	4424	0	0	0
T33	0	17	0	0
T54	0	16	0	0
T57	0	34	0	0
T63	0	6	0	0
T64	0	272	0	0
T65	0	52	0	0
T66	0	33	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	2618	0	0
T13	3511	0	0	0
T14	3106	0	0	0
T15	3577	0	0	0
T25	2900	6	0	0
T26	6414	0	0	0
T27	72790	258	0	0
T28	951	0	0	0
T29	1261	0	0	0
T30	4424	0	0	0
T33	0	11	0	0
T41	3455	0	0	0
T54	0	46	0	0
T57	0	23	0	0
T63	0	5	0	0
T64	0	251	0	0
T65	0	45	0	0
T66	0	61	0	0
T67	0	253	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	2621	0	0
T13	3511	0	0	0
T14	3106	0	0	0
T15	3577	0	0	0
T25	2900	15	0	0
T26	6414	0	0	0
T27	72790	229	0	0
T28	951	0	0	0
T29	1261	0	0	0
T30	4424	0	0	0
T33	0	30	0	0
T41	3455	0	0	0
T54	0	25	0	0
T57	0	33	0	0
T63	0	6	0	0
T64	0	323	0	0
T65	0	37	0	0
T66	0	86	0	0
T67	0	257	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	2411	0	0
T13	3511	0	0	0
T14	3106	0	0	0
T15	3577	0	0	0
T25	2900	8	0	0
T26	6414	0	0	0
T27	72790	226	0	0
T28	951	0	0	0
T29	1261	0	0	0
T30	4424	0	0	0
T33	0	22	0	0
T41	3455	0	0	0
T54	0	15	0	0
T57	0	40	0	0
T63	0	1	0	0
T64	0	203	0	0
T65	0	38	0	0
T66	0	38	0	0
T67	0	227	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555316	2512	0	0
T9	14531	6	0	0
T13	3511	0	0	0
T23	1752	0	0	0
T24	1409	0	0	0
T25	2900	7	0	0
T26	6414	0	0	0
T27	72790	259	0	0
T28	951	0	0	0
T29	1261	0	0	0
T30	4424	0	0	0
T33	0	26	0	0
T54	0	1	0	0
T57	0	32	0	0
T63	0	2	0	0
T64	0	212	0	0
T65	0	40	0	0
T66	0	54	0	0