Module Definition
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Module : prim_mubi4_sender
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sha3_done_sender 100.00 100.00 100.00 100.00
tb.dut.gen_entropy.u_entropy.u_entropy_configured 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_sha3_done_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.76 98.75 96.74 100.00 100.00 97.06 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00


Module Instance : tb.dut.gen_entropy.u_entropy.u_entropy_configured

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.57 100.00 87.83 100.00 100.00 100.00 gen_entropy.u_entropy


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00

Line Coverage for Module : prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1

Branch Coverage for Module : prim_mubi4_sender
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Module : prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 2147483647 2147483647 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 209316 209146 0 0
T2 149846 149676 0 0
T3 955150 955134 0 0
T4 42254 42056 0 0
T5 216954 216754 0 0
T10 2754 2610 0 0
T11 152894 152744 0 0
T12 245450 245436 0 0
T13 1940920 1940730 0 0
T14 408394 408380 0 0

Line Coverage for Instance : tb.dut.u_sha3_done_sender
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1

Branch Coverage for Instance : tb.dut.u_sha3_done_sender
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sha3_done_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 2147483647 2147483647 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 104658 104573 0 0
T2 74923 74838 0 0
T3 477575 477567 0 0
T4 21127 21028 0 0
T5 108477 108377 0 0
T10 1377 1305 0 0
T11 76447 76372 0 0
T12 122725 122718 0 0
T13 970460 970365 0 0
T14 204197 204190 0 0

Line Coverage for Instance : tb.dut.gen_entropy.u_entropy.u_entropy_configured
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1

Branch Coverage for Instance : tb.dut.gen_entropy.u_entropy.u_entropy_configured
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.gen_entropy.u_entropy.u_entropy_configured
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 2147483647 2147483647 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 104658 104573 0 0
T2 74923 74838 0 0
T3 477575 477567 0 0
T4 21127 21028 0 0
T5 108477 108377 0 0
T10 1377 1305 0 0
T11 76447 76372 0 0
T12 122725 122718 0 0
T13 970460 970365 0 0
T14 204197 204190 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%