Unified Coverage Report :: Module :: kmac

Module : kmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.76	98.75	96.74	100.00	100.00	97.06	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	98.76	98.75	96.74	100.00	100.00	97.06	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.76	98.75	96.74	100.00	100.00	97.06	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.68	98.10	92.71	99.89	94.55	95.97	98.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
gen_entropy.u_entropy	97.83	100.00	87.97	100.00	100.00	98.98	100.00
gen_entropy.u_prim_sync_reqack_data	95.83	100.00	83.33			100.00	100.00
intr_fifo_empty	86.94	90.00	77.78			80.00	100.00
intr_kmac_done	93.75	100.00	75.00			100.00	100.00
intr_kmac_err	93.75	100.00	75.00			100.00	100.00
kmac_csr_assert	100.00						100.00
sha3pad_assert_cov_if	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_app_intf	97.42	97.45	90.82		100.00	98.82	100.00
u_errchk	96.60	95.06	94.59		100.00	93.33	100.00
u_kmac_core	95.80	98.88	92.86	100.00	100.00	91.38	91.67
u_msgfifo	97.43	100.00	95.83	94.52	100.00	94.23	100.00
u_prim_lc_sync	100.00	100.00				100.00	100.00
u_reg	98.99	99.27	96.90	100.00		98.78	100.00
u_sha3	96.19	98.85	95.87	100.00	85.71	96.71	100.00
u_sha3_done_sender	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00
u_staterd	89.95	89.88	81.39			88.54	100.00
u_tlul_adapter_msgfifo	79.91	87.01	74.59			77.38	80.65

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : kmac

	Line No.	Total	Covered	Percent
TOTAL		160	158	98.75
ALWAYS	343	0	0
ALWAYS	343	2	2	100.00
ALWAYS	349	1	0	0.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
ALWAYS	426	9	9	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
ALWAYS	485	6	6	100.00
ALWAYS	498	6	6	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	540	1	1	100.00
CONT_ASSIGN	542	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
ALWAYS	558	5	5	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
CONT_ASSIGN	576	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	627	1	1	100.00
CONT_ASSIGN	633	1	1	100.00
CONT_ASSIGN	641	1	1	100.00
CONT_ASSIGN	646	1	1	100.00
ALWAYS	649	5	5	100.00
CONT_ASSIGN	678	1	1	100.00
CONT_ASSIGN	683	1	1	100.00
ALWAYS	686	7	7	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	727	1	1	100.00
CONT_ASSIGN	734	1	1	100.00
CONT_ASSIGN	744	1	1	100.00
ALWAYS	764	3	3	100.00
ALWAYS	768	28	28	100.00
ALWAYS	906	3	3	100.00
CONT_ASSIGN	914	1	1	100.00
CONT_ASSIGN	914	1	1	100.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	1023	1	1	100.00
CONT_ASSIGN	1028	1	1	100.00
CONT_ASSIGN	1029	1	1	100.00
CONT_ASSIGN	1031	1	1	100.00
CONT_ASSIGN	1034	0	0
ALWAYS	1152	0	0
ALWAYS	1152	2	2	100.00
CONT_ASSIGN	1238	1	1	100.00
CONT_ASSIGN	1381	1	1	100.00
CONT_ASSIGN	1395	1	1	100.00
CONT_ASSIGN	1402	1	1	100.00
CONT_ASSIGN	1407	1	1	100.00
ALWAYS	1413	6	5	83.33
CONT_ASSIGN	1422	1	1	100.00
CONT_ASSIGN	1424	1	1	100.00
ALWAYS	1436	4	4	100.00
CONT_ASSIGN	1442	1	1	100.00
ALWAYS	1465	4	4	100.00
ALWAYS	1475	3	3	100.00
CONT_ASSIGN	1486	1	1	100.00
CONT_ASSIGN	1490	1	1	100.00
CONT_ASSIGN	1492	1	1	100.00
CONT_ASSIGN	1492	1	1	100.00
CONT_ASSIGN	1492	1	1	100.00
CONT_ASSIGN	1492	1	1	100.00
CONT_ASSIGN	1492	1	1	100.00
CONT_ASSIGN	1492	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
343	1	1
344	1	1
349	0	1
418	1	1
419	1	1
423	1	1
426	1	1
427	1	1
428	1	1
429	1	1
431	1	1
433	1	1
437	1	1
441	1	1
445	1	1
461	1	1
462	1	1
463	1	1
466	1	1
470	1	1
471	1	1
475	1	1
478	1	1
485	1	1
486	1	1
487	1	1
488	1	1
489	1	1
490	1	1
			MISSING_ELSE
			MISSING_ELSE
498	1	1
499	1	1
500	1	1
501	1	1
502	1	1
503	1	1
			MISSING_ELSE
			MISSING_ELSE
515	1	1
522	1	1
525	1	1
526	1	1
527	1	1
529	1	1
530	1	1
532	1	1
534	1	1
536	1	1
540	1	1
542	1	1
543	1	1
546	1	1
547	1	1
550	1	1
558	1	1
559	1	1
560	1	1
561	1	1
563	1	1
568	1	1
575	1	1
576	1	1
577	1	1
585	1	1
627	1	1
633	1	1
641	1	1
646	1	1
649	1	1
650	1	1
651	1	1
653	1	1
654	1	1
678	1	1
683	1	1
686	1	1
688	1	1
693	1	1
697	1	1
701	1	1
705	1	1
709	1	1
722	1	1
727	1	1
734	1	1
744	1	1
764	3	3
768	1	1
770	1	1
771	1	1
773	1	1
775	1	1
777	1	1
778	1	1
781	1	1
784	1	1
790	1	1
791	1	1
793	1	1
798	1	1
799	1	1
800	1	1
802	1	1
808	1	1
813	1	1
814	1	1
816	1	1
818	1	1
824	1	1
825	1	1
827	1	1
833	1	1
834	1	1
846	1	1
847	1	1
			MISSING_ELSE
906	1	1
907	1	1
909	1	1
914	2	2
990	1	1
992	1	1
1023	1	1
1028	1	1
1029	1	1
1031	1	1
1034		unreachable
1152	1	1
1153	1	1
1238	1	1
1381	1	1
1395	1	1
1402	1	1
1407	1	1
1413	1	1
1414	1	1
1415	1	1
1416	0	1
1417	1	1
1418	1	1
			MISSING_ELSE
1422	1	1
1424	1	1
1436	1	1
1437	1	1
1438	1	1
1439	1	1
			MISSING_ELSE
1442	1	1
1465	1	1
1466	1	1
1467	1	1
1469	1	1
			MISSING_ELSE
1475	1	1
1476	1	1
1479	1	1
1486	1	1
1490	1	1
1492	6	6

---

Cond Coverage for Module : kmac

	Total	Covered	Percent
Conditions	92	89	96.74
Logical	92	89	96.74
Non-Logical	0	0
Event	0	0

 LINE       423
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       461
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       462
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       463
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       475
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       527
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T30

 LINE       536
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T30,T68

 LINE       540
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       547
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T3,T4,T5
1	1	1	Covered	T3,T4,T5

 LINE       560
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T16,T17,T89
1	1	Covered	T1,T2,T3

 LINE       560
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       560
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T3,T4,T5
1	-	Covered	T1,T2,T3

 LINE       568
 EXPRESSION (reg2hw.cfg_shadowed.err_processed.q & reg2hw.cfg_shadowed.err_processed.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T11

 LINE       627
 EXPRESSION (msgfifo_empty_q & ((~msgfifo_empty)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       633
 EXPRESSION (msgfifo_full ? 1'b1 : (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T6,T7

 LINE       633
 SUB-EXPRESSION (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q))
                 ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       633
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       641
 EXPRESSION (app_active ? 1'b1 : ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T11

 LINE       641
 SUB-EXPRESSION ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q))))
                 -----------1----------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       641
 SUB-EXPRESSION (sha3_fsm != StAbsorb)
                -----------1----------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       641
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))
                 ----------1---------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       646
 EXPRESSION (msgfifo_empty_gate ? 1'b0 : msgfifo_empty)
             ---------1--------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T1,T2,T3

 LINE       678
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T33,T34,T87
0	0	1	0	Covered	T69,T76,T70
0	1	0	0	Covered	T1,T2,T11
1	0	0	0	Covered	T7,T8,T29

 LINE       722
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T15,T16,T17
0	0	1	0	Covered	T15,T16,T17
0	1	0	0	Covered	T15,T16,T17
1	0	0	0	Covered	T15,T16,T17

 LINE       734
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T15,T16,T17
0	0	0	0	1	0	Covered	T15,T16,T17
0	0	0	1	0	0	Covered	T15,T16,T17
0	0	1	0	0	0	Covered	T15,T16,T17
0	1	0	0	0	0	Covered	T15,T16,T17
1	0	0	0	0	0	Covered	T15,T16,T17

 LINE       775
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       777
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T3,T5,T12
1	Covered	T4,T5,T12

 LINE       791
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T12,T13,T6
1	Covered	T4,T5,T12

 LINE       1023
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Covered	T3,T4,T5

 LINE       1153
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       1395
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T111,T112
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T111,T112

 LINE       1395
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T111,T112
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T111,T112

 LINE       1424
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T15,T16,T17
0	0	1	0	0	Covered	T25,T26,T27
0	1	0	0	0	Covered	T15,T16,T17
1	0	0	0	0	Not Covered

---

Toggle Coverage for Module : kmac

	Total	Covered	Percent
Totals	71	71	100.00
Total Bits	6534	6534	100.00
Total Bits 0->1	3267	3267	100.00
Total Bits 1->0	3267	3267	100.00

Ports	71	71	100.00
Port Bits	6534	6534	100.00
Port Bits 0->1	3267	3267	100.00
Port Bits 1->0	3267	3267	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T7,T8,T53	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T7,T8,T53	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T7,T8,T53	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T3,T10,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T11,T8	Yes	T4,T11,T8	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T8,T82,T60	Yes	T8,T82,T60	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T4,T5,T11	Yes	T1,T10,T4	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T10,T111,T112	Yes	T10,T111,T112	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T10,T25,T26	Yes	T10,T25,T26	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T10,T111,T112	Yes	T10,T111,T112	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T10,T25,T26	Yes	T10,T25,T26	OUTPUT
keymgr_key_i.key[1:0][255:0]	Yes	Yes	T5,T12,T13	Yes	T5,T12,T13	INPUT
keymgr_key_i.valid	Yes	Yes	T5,T12,T13	Yes	T5,T12,T13	INPUT
app_i[0].last	Yes	Yes	T12,T13,T6	Yes	T12,T13,T6	INPUT
app_i[0].strb[7:0]	Yes	Yes	T7,T8,T30	Yes	T7,T8,T30	INPUT
app_i[0].data[63:0]	Yes	Yes	T1,T2,T11	Yes	T1,T2,T11	INPUT
app_i[0].valid	Yes	Yes	T1,T2,T11	Yes	T1,T2,T11	INPUT
app_i[1].last	Yes	Yes	T12,T13,T6	Yes	T12,T13,T6	INPUT
app_i[1].strb[7:0]	Yes	Yes	T7,T8,T30	Yes	T7,T8,T30	INPUT
app_i[1].data[63:0]	Yes	Yes	T12,T13,T6	Yes	T12,T13,T6	INPUT
app_i[1].valid	Yes	Yes	T12,T13,T6	Yes	T12,T13,T6	INPUT
app_i[2].last	Yes	Yes	T12,T13,T7	Yes	T12,T13,T7	INPUT
app_i[2].strb[7:0]	Yes	Yes	T7,T8,T30	Yes	T7,T8,T30	INPUT
app_i[2].data[63:0]	Yes	Yes	T12,T13,T7	Yes	T12,T13,T7	INPUT
app_i[2].valid	Yes	Yes	T12,T13,T7	Yes	T12,T13,T7	INPUT
app_o[0].error	Yes	Yes	T7,T8,T20	Yes	T7,T8,T20	OUTPUT
app_o[0].digest_share1[383:0]	Yes	Yes	T12,T13,T6	Yes	T12,T13,T6	OUTPUT
app_o[0].digest_share0[383:0]	Yes	Yes	T12,T13,T6	Yes	T12,T13,T6	OUTPUT
app_o[0].done	Yes	Yes	T12,T13,T6	Yes	T12,T13,T6	OUTPUT
app_o[0].ready	Yes	Yes	T1,T2,T11	Yes	T1,T2,T11	OUTPUT
app_o[1].error	Yes	Yes	T7,T8,T29	Yes	T7,T8,T29	OUTPUT
app_o[1].digest_share1[383:0]	Yes	Yes	T12,T13,T6	Yes	T12,T13,T6	OUTPUT
app_o[1].digest_share0[383:0]	Yes	Yes	T12,T13,T6	Yes	T12,T13,T6	OUTPUT
app_o[1].done	Yes	Yes	T12,T13,T6	Yes	T12,T13,T6	OUTPUT
app_o[1].ready	Yes	Yes	T12,T13,T6	Yes	T12,T13,T6	OUTPUT
app_o[2].error	Yes	Yes	T7,T8,T29	Yes	T7,T8,T29	OUTPUT
app_o[2].digest_share1[383:0]	Yes	Yes	T12,T13,T7	Yes	T12,T13,T7	OUTPUT
app_o[2].digest_share0[383:0]	Yes	Yes	T12,T13,T7	Yes	T12,T13,T7	OUTPUT
app_o[2].done	Yes	Yes	T12,T13,T7	Yes	T12,T13,T7	OUTPUT
app_o[2].ready	Yes	Yes	T12,T13,T7	Yes	T12,T13,T7	OUTPUT
entropy_o.edn_req	Yes	Yes	T4,T5,T12	Yes	T4,T5,T12	OUTPUT
entropy_i.edn_bus[31:0]	Yes	Yes	T4,T5,T12	Yes	T4,T5,T12	INPUT
entropy_i.edn_fips	Yes	Yes	T4,T5,T13	Yes	T4,T5,T12	INPUT
entropy_i.edn_ack	Yes	Yes	T4,T5,T12	Yes	T4,T5,T12	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INPUT
intr_kmac_done_o	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
intr_fifo_empty_o	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT
intr_kmac_err_o	Yes	Yes	T1,T2,T11	Yes	T1,T2,T11	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : kmac

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	816	Covered	T3,T4,T5
KmacIdle	784	Covered	T1,T2,T3
KmacKeyBlock	791	Covered	T4,T5,T12
KmacMsgFeed	781	Covered	T3,T4,T5
KmacPrefix	778	Covered	T4,T5,T12
KmacTerminalError	833	Covered	T25,T26,T27

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	825	Covered	T3,T4,T5
KmacDigest->KmacTerminalError	847	Covered	T26,T40,T56
KmacIdle->KmacMsgFeed	781	Covered	T3,T5,T12
KmacIdle->KmacPrefix	778	Covered	T4,T5,T12
KmacIdle->KmacTerminalError	847	Covered	T39,T15,T16
KmacKeyBlock->KmacMsgFeed	800	Covered	T4,T5,T12
KmacKeyBlock->KmacTerminalError	847	Covered	T38,T46,T45
KmacMsgFeed->KmacDigest	816	Covered	T3,T4,T5
KmacMsgFeed->KmacIdle	813	Covered	T12,T13,T6
KmacMsgFeed->KmacTerminalError	847	Covered	T43,T54,T113
KmacPrefix->KmacKeyBlock	791	Covered	T4,T5,T12
KmacPrefix->KmacMsgFeed	791	Covered	T12,T13,T6
KmacPrefix->KmacTerminalError	847	Covered	T25,T27,T50

---

Branch Coverage for Module : kmac

	Line No.	Total	Covered	Percent
Branches		68	66	97.06
TERNARY	423	2	2	100.00
TERNARY	633	4	4	100.00
TERNARY	641	4	4	100.00
TERNARY	646	2	2	100.00
CASE	431	6	5	83.33
IF	485	3	3	100.00
IF	558	3	3	100.00
IF	649	2	2	100.00
CASE	688	6	6	100.00
IF	764	2	2	100.00
CASE	773	15	15	100.00
IF	846	2	2	100.00
TERNARY	1153	2	2	100.00
IF	1413	4	3	75.00
IF	1436	3	3	100.00
IF	1465	3	3	100.00
IF	1475	2	2	100.00
IF	498	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	423	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	633	(msgfifo_full) ? 
-2-:	633	(msgfifo_empty_negedge) ? 
-3-:	633	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T13,T6,T7
0	1	-	Covered	T3,T4,T5
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	641	(app_active) ? 
-2-:	641	((sha3_fsm != StAbsorb)) ? 
-3-:	641	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T11
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	646	(msgfifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	431	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Covered	T3,T4,T5
CmdProcess	Covered	T3,T4,T5
CmdManualRun	Covered	T12,T13,T6
CmdDone	Covered	T3,T4,T5
CmdNone	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	485	if ((!rst_ni))
-2-:	487	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	558	if ((!rst_ni))
-2-:	560	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	649	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	688	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Covered	T1,T2,T11
errchecker_err.valid	Covered	T33,T34,T87
sha3_err.valid	Covered	T7,T8,T29
entropy_err.valid	Covered	T69,T76,T70
msgfifo_err.valid	Covered	T15,T16,T17
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	764	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	773	case (kmac_st)
-2-:	775	if ((kmac_cmd == CmdStart))
-3-:	777	if ((CShake == app_sha3_mode))
-4-:	790	if (sha3_block_processed)
-5-:	791	(app_kmac_en) ? 
-6-:	799	if (sha3_block_processed)
-7-:	808	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	814	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	824	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T4,T5,T12
KmacIdle	1	0	-	-	-	-	-	-	Covered	T3,T5,T12
KmacIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T4,T5,T12
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T12,T13,T6
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T4,T5,T12
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T4,T5,T12
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T4,T5,T12
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T12,T13,T6
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T3,T4,T5
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T3,T4,T5
KmacDigest	-	-	-	-	-	-	-	1	Covered	T3,T4,T5
KmacDigest	-	-	-	-	-	-	-	0	Covered	T3,T4,T5
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T25,T26,T27
default	-	-	-	-	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	846	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Covered	T25,T26,T27
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1153	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1413	if ((!rst_ni))
-2-:	1415	if (alert_recov_operation)
-3-:	1417	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1436	if ((!rst_ni))
-2-:	1438	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T25,T26,T27
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1465	if ((!rst_ni))
-2-:	1467	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T25,T26,T27
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1475	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	498	if ((!rst_ni))
-2-:	500	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T3,T4,T5

---

Assert Coverage for Module : kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	35	35	100.00	35	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	35	35	100.00	35	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	2147483647	2147483647	0	0
CmdSparse_M	2147483647	1281972	0	0
EnMaskingKnown_A	2147483647	2147483647	0	0
EntropyReadyLatched_A	2147483647	337910	0	0
EntrySizeRegSameToEntrySizePkg_A	1032	1032	0	0
ErrProcessedLatched_A	2147483647	812	0	0
FifoEmpty_A	2147483647	2147483647	0	0
FpvSecCmErrorCheckFsmCheck_A	2147483647	80	0	0
FpvSecCmKeccackFsmCheck_A	2147483647	80	0	0
FpvSecCmKeyIndexCountCheck_A	2147483647	80	0	0
FpvSecCmKmacAppFsmCheck_A	2147483647	80	0	0
FpvSecCmKmacCoreFsmCheck_A	2147483647	80	0	0
FpvSecCmKmacFsmCheck_A	2147483647	80	0	0
FpvSecCmRegWeOnehotCheck_A	2147483647	80	0	0
FpvSecCmRoundCountCheck_A	2147483647	80	0	0
FpvSecCmSHA3FsmCheck_A	2147483647	80	0	0
FpvSecCmSHA3padFsmCheck_A	2147483647	80	0	0
FpvSecCmSentMsgCountCheck_A	2147483647	80	0	0
KmacCmd_A	2147483647	2147483647	0	0
KmacDone_A	2147483647	2147483647	0	0
KmacErr_A	2147483647	2147483647	0	0
KmacStKnown_A	2147483647	2147483647	0	0
NumAlerts2_A	1032	1032	0	0
NumEntriesRegSameToNumEntriesPkg_A	1032	1032	0	0
PrefixRegSameToPrefixPkg_A	1032	1032	0	0
SecretKeyDivideBy32_A	1032	1032	0	0
Sha3AbsorbedPulse_A	2147483647	347072	0	0
TlOAReadyKnown_A	2147483647	2147483647	0	0
TlODValidKnown_A	2147483647	2147483647	0	0
g_testassertion.FpvSecCmEntropyFsmCheck_A	2147483647	80	0	0
g_testassertion.FpvSecCmHashCountCheck_A	2147483647	80	0	0
g_testassertion.FpvSecCmMsgFifoRptrCheck_A	2147483647	80	0	0
g_testassertion.FpvSecCmMsgFifoWptrCheck_A	2147483647	80	0	0
g_testassertion.FpvSecCmPackerCountCheck_A	2147483647	80	0	0
u_state_regs_A	2147483647	2147483647	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	104658	104573	0	0
T2	74923	74838	0	0
T3	477575	477567	0	0
T4	21127	21028	0	0
T5	108477	108377	0	0
T10	1377	1305	0	0
T11	76447	76372	0	0
T12	122725	122718	0	0
T13	970460	970365	0	0
T14	204197	204190	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1281972	0	0
T1	104658	4	0	0
T2	74923	4	0	0
T3	477575	991	0	0
T4	21127	30	0	0
T5	108477	363	0	0
T6	0	383	0	0
T10	1377	0	0	0
T11	76447	2	0	0
T12	122725	743	0	0
T13	970460	746	0	0
T14	204197	1249	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	104658	104573	0	0
T2	74923	74838	0	0
T3	477575	477567	0	0
T4	21127	21028	0	0
T5	108477	108377	0	0
T10	1377	1305	0	0
T11	76447	76372	0	0
T12	122725	122718	0	0
T13	970460	970365	0	0
T14	204197	204190	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	337910	0	0
T1	104658	18	0	0
T2	74923	13	0	0
T3	477575	300	0	0
T4	21127	9	0	0
T5	108477	112	0	0
T6	0	72	0	0
T10	1377	0	0	0
T11	76447	14	0	0
T12	122725	136	0	0
T13	970460	131	0	0
T14	204197	379	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032	1032	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	812	0	0
T1	104658	18	0	0
T2	74923	13	0	0
T3	477575	0	0	0
T4	21127	0	0	0
T5	108477	0	0	0
T10	1377	0	0	0
T11	76447	14	0	0
T12	122725	0	0	0
T13	970460	0	0	0
T14	204197	0	0	0
T20	0	11	0	0
T69	0	6	0	0
T76	0	11	0	0
T114	0	19	0	0
T115	0	8	0	0
T116	0	12	0	0
T117	0	15	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	104658	104573	0	0
T2	74923	74838	0	0
T3	477575	477567	0	0
T4	21127	21028	0	0
T5	108477	108377	0	0
T10	1377	1305	0	0
T11	76447	76372	0	0
T12	122725	122718	0	0
T13	970460	970365	0	0
T14	204197	204190	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T15	894258	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T89	0	20	0	0
T118	0	10	0	0
T119	901835	0	0	0
T120	21373	0	0	0
T121	601407	0	0	0
T122	1712	0	0	0
T123	289952	0	0	0
T124	260102	0	0	0
T125	150048	0	0	0
T126	227332	0	0	0
T127	186295	0	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T15	894258	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T89	0	20	0	0
T118	0	10	0	0
T119	901835	0	0	0
T120	21373	0	0	0
T121	601407	0	0	0
T122	1712	0	0	0
T123	289952	0	0	0
T124	260102	0	0	0
T125	150048	0	0	0
T126	227332	0	0	0
T127	186295	0	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T15	894258	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T89	0	20	0	0
T118	0	10	0	0
T119	901835	0	0	0
T120	21373	0	0	0
T121	601407	0	0	0
T122	1712	0	0	0
T123	289952	0	0	0
T124	260102	0	0	0
T125	150048	0	0	0
T126	227332	0	0	0
T127	186295	0	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T15	894258	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T89	0	20	0	0
T118	0	10	0	0
T119	901835	0	0	0
T120	21373	0	0	0
T121	601407	0	0	0
T122	1712	0	0	0
T123	289952	0	0	0
T124	260102	0	0	0
T125	150048	0	0	0
T126	227332	0	0	0
T127	186295	0	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T15	894258	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T89	0	20	0	0
T118	0	10	0	0
T119	901835	0	0	0
T120	21373	0	0	0
T121	601407	0	0	0
T122	1712	0	0	0
T123	289952	0	0	0
T124	260102	0	0	0
T125	150048	0	0	0
T126	227332	0	0	0
T127	186295	0	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T15	894258	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T89	0	20	0	0
T118	0	10	0	0
T119	901835	0	0	0
T120	21373	0	0	0
T121	601407	0	0	0
T122	1712	0	0	0
T123	289952	0	0	0
T124	260102	0	0	0
T125	150048	0	0	0
T126	227332	0	0	0
T127	186295	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T15	894258	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T89	0	20	0	0
T118	0	10	0	0
T119	901835	0	0	0
T120	21373	0	0	0
T121	601407	0	0	0
T122	1712	0	0	0
T123	289952	0	0	0
T124	260102	0	0	0
T125	150048	0	0	0
T126	227332	0	0	0
T127	186295	0	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T15	894258	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T89	0	20	0	0
T118	0	10	0	0
T119	901835	0	0	0
T120	21373	0	0	0
T121	601407	0	0	0
T122	1712	0	0	0
T123	289952	0	0	0
T124	260102	0	0	0
T125	150048	0	0	0
T126	227332	0	0	0
T127	186295	0	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T15	894258	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T89	0	20	0	0
T118	0	10	0	0
T119	901835	0	0	0
T120	21373	0	0	0
T121	601407	0	0	0
T122	1712	0	0	0
T123	289952	0	0	0
T124	260102	0	0	0
T125	150048	0	0	0
T126	227332	0	0	0
T127	186295	0	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T15	894258	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T89	0	20	0	0
T118	0	10	0	0
T119	901835	0	0	0
T120	21373	0	0	0
T121	601407	0	0	0
T122	1712	0	0	0
T123	289952	0	0	0
T124	260102	0	0	0
T125	150048	0	0	0
T126	227332	0	0	0
T127	186295	0	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T15	894258	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T89	0	20	0	0
T118	0	10	0	0
T119	901835	0	0	0
T120	21373	0	0	0
T121	601407	0	0	0
T122	1712	0	0	0
T123	289952	0	0	0
T124	260102	0	0	0
T125	150048	0	0	0
T126	227332	0	0	0
T127	186295	0	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	104658	104573	0	0
T2	74923	74838	0	0
T3	477575	477567	0	0
T4	21127	21028	0	0
T5	108477	108377	0	0
T10	1377	1305	0	0
T11	76447	76372	0	0
T12	122725	122718	0	0
T13	970460	970365	0	0
T14	204197	204190	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	104658	104573	0	0
T2	74923	74838	0	0
T3	477575	477567	0	0
T4	21127	21028	0	0
T5	108477	108377	0	0
T10	1377	1305	0	0
T11	76447	76372	0	0
T12	122725	122718	0	0
T13	970460	970365	0	0
T14	204197	204190	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	104658	104573	0	0
T2	74923	74838	0	0
T3	477575	477567	0	0
T4	21127	21028	0	0
T5	108477	108377	0	0
T10	1377	1305	0	0
T11	76447	76372	0	0
T12	122725	122718	0	0
T13	970460	970365	0	0
T14	204197	204190	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	104658	104573	0	0
T2	74923	74838	0	0
T3	477575	477567	0	0
T4	21127	21028	0	0
T5	108477	108377	0	0
T10	1377	1305	0	0
T11	76447	76372	0	0
T12	122725	122718	0	0
T13	970460	970365	0	0
T14	204197	204190	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032	1032	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032	1032	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032	1032	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032	1032	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347072	0	0
T3	477575	310	0	0
T4	21127	9	0	0
T5	108477	113	0	0
T6	228729	72	0	0
T7	200867	477	0	0
T8	0	310	0	0
T10	1377	0	0	0
T11	76447	0	0	0
T12	122725	137	0	0
T13	970460	132	0	0
T14	204197	390	0	0
T18	0	146	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	104658	104573	0	0
T2	74923	74838	0	0
T3	477575	477567	0	0
T4	21127	21028	0	0
T5	108477	108377	0	0
T10	1377	1305	0	0
T11	76447	76372	0	0
T12	122725	122718	0	0
T13	970460	970365	0	0
T14	204197	204190	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	104658	104573	0	0
T2	74923	74838	0	0
T3	477575	477567	0	0
T4	21127	21028	0	0
T5	108477	108377	0	0
T10	1377	1305	0	0
T11	76447	76372	0	0
T12	122725	122718	0	0
T13	970460	970365	0	0
T14	204197	204190	0	0

g_testassertion.FpvSecCmEntropyFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T15	894258	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T89	0	20	0	0
T118	0	10	0	0
T119	901835	0	0	0
T120	21373	0	0	0
T121	601407	0	0	0
T122	1712	0	0	0
T123	289952	0	0	0
T124	260102	0	0	0
T125	150048	0	0	0
T126	227332	0	0	0
T127	186295	0	0	0

g_testassertion.FpvSecCmHashCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T15	894258	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T89	0	20	0	0
T118	0	10	0	0
T119	901835	0	0	0
T120	21373	0	0	0
T121	601407	0	0	0
T122	1712	0	0	0
T123	289952	0	0	0
T124	260102	0	0	0
T125	150048	0	0	0
T126	227332	0	0	0
T127	186295	0	0	0

g_testassertion.FpvSecCmMsgFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T15	894258	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T89	0	20	0	0
T118	0	10	0	0
T119	901835	0	0	0
T120	21373	0	0	0
T121	601407	0	0	0
T122	1712	0	0	0
T123	289952	0	0	0
T124	260102	0	0	0
T125	150048	0	0	0
T126	227332	0	0	0
T127	186295	0	0	0

g_testassertion.FpvSecCmMsgFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T15	894258	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T89	0	20	0	0
T118	0	10	0	0
T119	901835	0	0	0
T120	21373	0	0	0
T121	601407	0	0	0
T122	1712	0	0	0
T123	289952	0	0	0
T124	260102	0	0	0
T125	150048	0	0	0
T126	227332	0	0	0
T127	186295	0	0	0

g_testassertion.FpvSecCmPackerCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T15	894258	20	0	0
T16	0	10	0	0
T17	0	20	0	0
T89	0	20	0	0
T118	0	10	0	0
T119	901835	0	0	0
T120	21373	0	0	0
T121	601407	0	0	0
T122	1712	0	0	0
T123	289952	0	0	0
T124	260102	0	0	0
T125	150048	0	0	0
T126	227332	0	0	0
T127	186295	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	104658	104573	0	0
T2	74923	74838	0	0
T3	477575	477567	0	0
T4	21127	21028	0	0
T5	108477	108377	0	0
T10	1377	1305	0	0
T11	76447	76372	0	0
T12	122725	122718	0	0
T13	970460	970365	0	0
T14	204197	204190	0	0