Unified Coverage Report :: Module :: kmac_app

Module : kmac_app

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.80	98.92	89.47		72.00	98.59	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_app.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_app_intf	97.40	98.92	89.47		100.00	98.59	100.00

---

Module Instance : tb.dut.u_app_intf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.40	98.92	89.47		100.00	98.59	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.42	97.45	90.82		100.00	98.82	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_appid_arb	95.05	87.50	92.68			100.00	100.00
u_prim_buf_state_err_check	100.00	100.00
u_prim_buf_state_kmac_sel	100.00	100.00
u_prim_buf_state_output_sel	100.00	100.00
u_prim_buf_state_output_valid	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : kmac_app

	Line No.	Total	Covered	Percent
TOTAL		186	184	98.92
ALWAYS	294	6	6	100.00
ALWAYS	308	0	0
ALWAYS	308	4	4	100.00
ALWAYS	333	6	6	100.00
ALWAYS	352	3	3	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
ALWAYS	380	3	3	100.00
ALWAYS	389	3	3	100.00
ALWAYS	392	1	0	0.00
ALWAYS	397	73	73	100.00
ALWAYS	604	18	18	100.00
ALWAYS	648	5	5	100.00
CONT_ASSIGN	668	1	1	100.00
CONT_ASSIGN	679	1	1	100.00
CONT_ASSIGN	690	1	1	100.00
ALWAYS	712	13	13	100.00
ALWAYS	737	6	6	100.00
CONT_ASSIGN	761	1	1	100.00
CONT_ASSIGN	761	1	1	100.00
ALWAYS	775	11	11	100.00
ALWAYS	805	8	7	87.50
ALWAYS	834	16	16	100.00
ALWAYS	861	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_app.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_app.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
294	2	2
295	2	2
296	2	2
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
320	1	1
333	2	2
334	2	2
335	2	2
			MISSING_ELSE
352	1	1
353	1	1
354	1	1
376	1	1
377	1	1
380	2	2
381	1	1
389	3	3
392	0	1
397	1	1
399	1	1
402	1	1
403	1	1
406	1	1
409	1	1
412	1	1
413	1	1
415	1	1
416	1	1
419	1	1
420	1	1
422	1	1
424	1	1
425	1	1
428	1	1
429	1	1
430	1	1
432	1	1
434	1	1
439	1	1
446	1	1
448	1	1
450	1	1
452	1	1
459	1	1
462	1	1
467	1	1
468	1	1
469	1	1
470	1	1
472	1	1
475	1	1
480	1	1
482	1	1
483	1	1
485	1	1
490	1	1
491	1	1
495	1	1
497	1	1
498	1	1
500	1	1
502	1	1
507	1	1
509	1	1
510	1	1
512	1	1
513	1	1
515	1	1
520	1	1
524	1	1
525	1	1
526	1	1
531	1	1
533	1	1
535	1	1
536	1	1
539	1	1
			MISSING_ELSE
542	1	1
544	1	1
546	1	1
550	1	1
			MISSING_ELSE
			MISSING_ELSE
559	1	1
561	1	1
562	1	1
567	1	1
568	1	1
569	1	1
570	1	1
571	1	1
583	1	1
584	1	1
			MISSING_ELSE
604	1	1
605	1	1
607	1	1
608	1	1
609	1	1
611	1	1
614	1	1
615	1	1
617	1	1
618	1	1
620	1	1
625	1	1
626	1	1
627	1	1
631	1	1
632	1	1
633	1	1
634	1	1
648	1	1
650	1	1
652	1	1
657	1	1
659	1	1
			MISSING_ELSE
668	1	1
679	1	1
690	1	1
712	1	1
713	1	1
714	1	1
716	1	1
717	1	1
720	1	1
721	1	1
722	1	1
723	1	1
724	1	1
725	1	1
726	1	1
727	1	1
			MISSING_ELSE
			MISSING_ELSE
737	1	1
738	1	1
739	1	1
742	1	1
745	1	1
747	1	1
			MISSING_ELSE
761	2	2
775	1	1
776	1	1
777	1	1
780	1	1
782	1	1
783	1	1
784	1	1
789	1	1
790	1	1
791	1	1
792	1	1
			MISSING_ELSE
805	1	1
807	1	1
810	1	1
811	1	1
812	1	1
813	0	1
815	1	1
			MISSING_ELSE
822	1	1
834	1	1
835	1	1
836	1	1
837	1	1
838	1	1
840	1	1
841	1	1
842	1	1
843	1	1
844	1	1
845	1	1
847	1	1
848	1	1
849	1	1
850	1	1
851	1	1
			MISSING_ELSE
861	1	1
862	1	1
863	1	1

---

Cond Coverage for Module : kmac_app

	Total	Covered	Percent
Conditions	57	51	89.47
Logical	57	51	89.47
Non-Logical	0	0
Event	0	0

 LINE       309
 EXPRESSION (i == app_id)
            ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       310
 EXPRESSION (app_data_ready | fsm_data_ready)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T11
1	0	Covered	T12,T13,T6

 LINE       310
 EXPRESSION (app_digest_done | fsm_digest_done_q)
             -------1-------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T21,T22
1	0	Covered	T12,T13,T6

 LINE       310
 EXPRESSION (error_i | fsm_digest_done_q | sparse_fsm_error_o | service_rejected_error)
             ---1---   --------2--------   ---------3--------   -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T21,T23,T24
0	0	1	0	Covered	T25,T26,T27
0	1	0	0	Covered	T20,T22,T28
1	0	0	0	Covered	T7,T8,T29

 LINE       429
 EXPRESSION (sw_cmd_i == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       450
 EXPRESSION ((kmac_pkg::AppCfg[app_id].Mode == AppKMAC) && ((!keymgr_key_i.valid)))
             ---------------------1--------------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T6
1	0	Covered	T12,T13,T6
1	1	Covered	T1,T2,T11

 LINE       450
 SUB-EXPRESSION (kmac_pkg::AppCfg[app_id].Mode == AppKMAC)
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T12,T13,T6
1	Covered	T1,T2,T11

 LINE       468
 EXPRESSION (app_i[app_id].valid && app_o[app_id].ready && app_i[app_id].last)
             ---------1---------    ---------2---------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T30,T31,T32
1	1	0	Covered	T12,T13,T6
1	1	1	Covered	T12,T13,T6

 LINE       469
 EXPRESSION (kmac_pkg::AppCfg[app_id].Mode == AppKMAC)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T12,T13,T6
1	Covered	T12,T13,T6

 LINE       482
 EXPRESSION (kmac_valid_o && kmac_ready_i)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable	T7,T8,T30
1	1	Covered	T12,T13,T6

 LINE       512
 EXPRESSION (sw_cmd_i == CmdDone)
            ----------1----------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       542
 EXPRESSION (app_i[app_id].valid && app_i[app_id].last)
             ---------1---------    ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T11
1	1	Covered	T20,T21,T22

 LINE       650
 EXPRESSION ((mux_sel_buf_err_check != SelSw) && sw_valid_i)
             ----------------1---------------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T33,T34,T25

 LINE       650
 SUB-EXPRESSION (mux_sel_buf_err_check != SelSw)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       657
 EXPRESSION (app_active_o && (sw_cmd_i != CmdNone))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T11
1	1	Covered	T34,T35,T36

 LINE       657
 SUB-EXPRESSION (sw_cmd_i != CmdNone)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       811
 EXPRESSION (app_id == i)
            ------1------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T1,T2,T11

 LINE       812
 EXPRESSION (kmac_pkg::AppCfg[i].PrefixMode == 1'b0)
            --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Not Covered

 LINE       844
 EXPRESSION ((kmac_pkg::AppCfg[arb_idx].Mode == AppKMAC) ? 1'b1 : 1'b0)
             ---------------------1---------------------

-1-	Status	Tests
0	Covered	T12,T13,T6
1	Covered	T1,T2,T11

 LINE       844
 SUB-EXPRESSION (kmac_pkg::AppCfg[arb_idx].Mode == AppKMAC)
                ---------------------1---------------------

-1-	Status	Tests
0	Covered	T12,T13,T6
1	Covered	T1,T2,T11

 LINE       845
 EXPRESSION ((kmac_pkg::AppCfg[arb_idx].Mode == AppSHA3) ? Sha3 : CShake)
             ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Not Covered

 LINE       845
 SUB-EXPRESSION (kmac_pkg::AppCfg[arb_idx].Mode == AppSHA3)
                ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Not Covered

 LINE       848
 EXPRESSION (st == StIdle)
            -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : kmac_app

Summary for FSM :: st

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	25	18	72.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAppCfg	425	Covered	T1,T2,T11
StAppMsg	459	Covered	T12,T13,T6
StAppOutLen	470	Covered	T12,T13,T6
StAppProcess	472	Covered	T12,T13,T6
StAppWait	491	Covered	T12,T13,T6
StError	446	Covered	T1,T2,T11
StIdle	434	Covered	T1,T2,T3
StKeyMgrErrKeyNotValid	452	Covered	T1,T2,T11
StServiceRejectedError	550	Covered	T21,T23,T24
StSw	430	Covered	T3,T4,T5
StTerminalError	584	Covered	T25,T26,T27

transitions	Line No.	Covered	Tests
StAppCfg->StAppMsg	459	Covered	T12,T13,T6
StAppCfg->StError	446	Covered	T21,T23,T24
StAppCfg->StKeyMgrErrKeyNotValid	452	Covered	T1,T2,T11
StAppCfg->StTerminalError	584	Not Covered
StAppMsg->StAppOutLen	470	Covered	T12,T13,T6
StAppMsg->StAppProcess	472	Covered	T12,T13,T6
StAppMsg->StTerminalError	584	Covered	T25,T37,T38
StAppOutLen->StAppProcess	483	Covered	T12,T13,T6
StAppOutLen->StTerminalError	584	Not Covered
StAppProcess->StAppWait	491	Covered	T12,T13,T6
StAppProcess->StTerminalError	584	Not Covered
StAppWait->StIdle	497	Covered	T12,T13,T6
StAppWait->StTerminalError	584	Not Covered
StError->StIdle	536	Covered	T1,T2,T11
StError->StServiceRejectedError	550	Covered	T21,T23,T24
StError->StTerminalError	584	Not Covered
StIdle->StAppCfg	425	Covered	T1,T2,T11
StIdle->StSw	430	Covered	T3,T4,T5
StIdle->StTerminalError	584	Covered	T39,T15,T16
StKeyMgrErrKeyNotValid->StError	520	Covered	T1,T2,T11
StKeyMgrErrKeyNotValid->StTerminalError	584	Not Covered
StServiceRejectedError->StIdle	559	Covered	T21,T23,T24
StServiceRejectedError->StTerminalError	584	Not Covered
StSw->StIdle	513	Covered	T3,T4,T5
StSw->StTerminalError	584	Covered	T26,T27,T40

---

Branch Coverage for Module : kmac_app

	Line No.	Total	Covered	Percent
Branches		71	70	98.59
IF	294	4	4	100.00
IF	309	2	2	100.00
IF	333	4	4	100.00
IF	380	2	2	100.00
IF	389	2	2	100.00
CASE	422	25	25	100.00
IF	583	2	2	100.00
CASE	611	4	4	100.00
IF	650	3	3	100.00
IF	714	3	3	100.00
IF	739	2	2	100.00
CASE	780	4	4	100.00
CASE	807	3	3	100.00
IF	834	8	7	87.50
CASE	861	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_app.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_app.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	294	if ((!rst_ni))
-2-:	295	if (service_rejected_error_set)
-3-:	296	if (service_rejected_error_clr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T21,T23,T24
0	0	1	Covered	T21,T23,T24
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	309	if ((i == app_id))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	333	if ((!rst_ni))
-2-:	334	if (clr_appid)
-3-:	335	if (set_appid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T11
0	0	1	Covered	T1,T2,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	380	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	389	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	422	case (st)
-2-:	424	if (arb_valid)
-3-:	429	if ((sw_cmd_i == CmdStart))
-4-:	439	if (((kmac_pkg::AppCfg[app_id].Mode == AppKMAC) && prim_mubi_pkg::mubi4_test_false_strict(entropy_ready_i)))
-5-:	450	if (((kmac_pkg::AppCfg[app_id].Mode == AppKMAC) && (!keymgr_key_i.valid)))
-6-:	468	if (((app_i[app_id].valid && app_o[app_id].ready) && app_i[app_id].last))
-7-:	469	if ((kmac_pkg::AppCfg[app_id].Mode == AppKMAC))
-8-:	482	if ((kmac_valid_o && kmac_ready_i))
-9-:	495	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_i))
-10-:	512	if ((sw_cmd_i == CmdDone))
-11-:	535	if (err_processed_i)
-12-:	542	if ((app_i[app_id].valid && app_i[app_id].last))
-13-:	546	if (service_rejected_error)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
StIdle	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StAppCfg	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T21,T23,T24
StAppCfg	-	-	0	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
StAppCfg	-	-	0	0	-	-	-	-	-	-	-	-	Covered	T12,T13,T6
StAppMsg	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T12,T13,T6
StAppMsg	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T12,T13,T6
StAppMsg	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T12,T13,T6
StAppOutLen	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T12,T13,T6
StAppOutLen	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T7,T8,T30
StAppProcess	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T6
StAppWait	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T12,T13,T6
StAppWait	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T12,T13,T6
StSw	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T3,T4,T5
StSw	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T3,T4,T5
StKeyMgrErrKeyNotValid	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
StError	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T2,T11
StError	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T11
StError	-	-	-	-	-	-	-	-	-	-	1	1	Covered	T21,T23,T24
StError	-	-	-	-	-	-	-	-	-	-	1	0	Covered	T20,T22,T28
StError	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T11
StServiceRejectedError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T23,T24
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T26,T27
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	583	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T25,T26,T27
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	611	case (mux_sel_buf_kmac)

Branches:

-1-	Status	Tests
SelApp	Covered	T12,T13,T6
SelOutLen	Covered	T12,T13,T6
SelSw	Covered	T3,T4,T5
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	650	if (((mux_sel_buf_err_check != SelSw) && sw_valid_i))
-2-:	657	if ((app_active_o && (sw_cmd_i != CmdNone)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T33,T34,T25
0	1	Covered	T34,T35,T36
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	714	if (((mux_sel_buf_output == SelSw) && lc_ctrl_pkg::lc_tx_test_false_strict(lc_escalate_en_i)))
-2-:	720	if (keymgr_key_en_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T12,T13,T6
1	0	Covered	T3,T4,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	739	if ((((st == StAppWait) && prim_mubi_pkg::mubi4_test_true_strict(absorbed_i)) && lc_ctrl_pkg::lc_tx_test_false_strict(lc_escalate_en_i)))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	780	case (st)
-2-:	789	if (keymgr_key_en_i)

Branches:

-1-	-2-	Status	Tests
StAppCfg StAppMsg StAppOutLen StAppProcess StAppWait	-	Covered	T1,T2,T11
StSw	1	Covered	T12,T13,T6
StSw	0	Covered	T3,T4,T5
default	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	807	case (st)

Branches:

-1-	Status	Tests
StAppCfg StAppMsg StAppOutLen StAppProcess StAppWait	Covered	T1,T2,T11
StSw	Covered	T3,T4,T5
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	834	if ((!rst_ni))
-2-:	838	if (clr_appid)
-3-:	843	if (set_appid)
-4-:	844	((kmac_pkg::AppCfg[arb_idx].Mode == AppKMAC)) ? 
-5-:	845	((kmac_pkg::AppCfg[arb_idx].Mode == AppSHA3)) ? 
-6-:	848	if ((st == StIdle))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T2,T11
0	0	1	1	-	-	Covered	T1,T2,T11
0	0	1	0	-	-	Covered	T12,T13,T6
0	0	1	-	1	-	Not Covered
0	0	1	-	0	-	Covered	T1,T2,T11
0	0	0	-	-	1	Covered	T1,T2,T3
0	0	0	-	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	861	case ({fsm_err.valid, mux_err.valid})

Branches:

-1-	Status	Tests
2'bz1	Covered	T33,T34,T25
2'b10	Covered	T1,T2,T11
default	Covered	T1,T2,T3

---

Assert Coverage for Module : kmac_app

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	1	1	100.00	1	100.00
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AppIntfInRange_A	1032	1032	0	0
SideloadKeySameToDigest_A	1032	1032	0	0
u_state_regs_A	2147483647	2147483647	0	0

AppIntfInRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032	1032	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

SideloadKeySameToDigest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032	1032	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	104658	104573	0	0
T2	74923	74838	0	0
T3	477575	477567	0	0
T4	21127	21028	0	0
T5	108477	108377	0	0
T10	1377	1305	0	0
T11	76447	76372	0	0
T12	122725	122718	0	0
T13	970460	970365	0	0
T14	204197	204190	0	0

---

Cover Directives for Properties: Details

Name	Attempts	Matches	Incomplete
AppIntfUseDifferentSizeKey_C	2147483647	2560	0

AppIntfUseDifferentSizeKey_C

Name	Attempts	Matches	Incomplete
Total	2147483647	2560	0
T1	104658	10	0
T2	74923	11	0
T3	477575	0	0
T4	21127	0	0
T5	108477	0	0
T6	0	12	0
T7	0	21	0
T8	0	6	0
T10	1377	0	0
T11	76447	11	0
T12	122725	15	0
T13	970460	12	0
T14	204197	0	0
T33	0	1	0
T41	0	11	0

Line Coverage for Instance : tb.dut.u_app_intf

	Line No.	Total	Covered	Percent
TOTAL		186	184	98.92
ALWAYS	294	6	6	100.00
ALWAYS	308	0	0
ALWAYS	308	4	4	100.00
ALWAYS	333	6	6	100.00
ALWAYS	352	3	3	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
ALWAYS	380	3	3	100.00
ALWAYS	389	3	3	100.00
ALWAYS	392	1	0	0.00
ALWAYS	397	73	73	100.00
ALWAYS	604	18	18	100.00
ALWAYS	648	5	5	100.00
CONT_ASSIGN	668	1	1	100.00
CONT_ASSIGN	679	1	1	100.00
CONT_ASSIGN	690	1	1	100.00
ALWAYS	712	13	13	100.00
ALWAYS	737	6	6	100.00
CONT_ASSIGN	761	1	1	100.00
CONT_ASSIGN	761	1	1	100.00
ALWAYS	775	11	11	100.00
ALWAYS	805	8	7	87.50
ALWAYS	834	16	16	100.00
ALWAYS	861	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_app.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_app.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
294	2	2
295	2	2
296	2	2
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
320	1	1
333	2	2
334	2	2
335	2	2
			MISSING_ELSE
352	1	1
353	1	1
354	1	1
376	1	1
377	1	1
380	2	2
381	1	1
389	3	3
392	0	1
397	1	1
399	1	1
402	1	1
403	1	1
406	1	1
409	1	1
412	1	1
413	1	1
415	1	1
416	1	1
419	1	1
420	1	1
422	1	1
424	1	1
425	1	1
428	1	1
429	1	1
430	1	1
432	1	1
434	1	1
439	1	1
446	1	1
448	1	1
450	1	1
452	1	1
459	1	1
462	1	1
467	1	1
468	1	1
469	1	1
470	1	1
472	1	1
475	1	1
480	1	1
482	1	1
483	1	1
485	1	1
490	1	1
491	1	1
495	1	1
497	1	1
498	1	1
500	1	1
502	1	1
507	1	1
509	1	1
510	1	1
512	1	1
513	1	1
515	1	1
520	1	1
524	1	1
525	1	1
526	1	1
531	1	1
533	1	1
535	1	1
536	1	1
539	1	1
			MISSING_ELSE
542	1	1
544	1	1
546	1	1
550	1	1
			MISSING_ELSE
			MISSING_ELSE
559	1	1
561	1	1
562	1	1
567	1	1
568	1	1
569	1	1
570	1	1
571	1	1
583	1	1
584	1	1
			MISSING_ELSE
604	1	1
605	1	1
607	1	1
608	1	1
609	1	1
611	1	1
614	1	1
615	1	1
617	1	1
618	1	1
620	1	1
625	1	1
626	1	1
627	1	1
631	1	1
632	1	1
633	1	1
634	1	1
648	1	1
650	1	1
652	1	1
657	1	1
659	1	1
			MISSING_ELSE
668	1	1
679	1	1
690	1	1
712	1	1
713	1	1
714	1	1
716	1	1
717	1	1
720	1	1
721	1	1
722	1	1
723	1	1
724	1	1
725	1	1
726	1	1
727	1	1
			MISSING_ELSE
			MISSING_ELSE
737	1	1
738	1	1
739	1	1
742	1	1
745	1	1
747	1	1
			MISSING_ELSE
761	2	2
775	1	1
776	1	1
777	1	1
780	1	1
782	1	1
783	1	1
784	1	1
789	1	1
790	1	1
791	1	1
792	1	1
			MISSING_ELSE
805	1	1
807	1	1
810	1	1
811	1	1
812	1	1
813	0	1
815	1	1
			MISSING_ELSE
822	1	1
834	1	1
835	1	1
836	1	1
837	1	1
838	1	1
840	1	1
841	1	1
842	1	1
843	1	1
844	1	1
845	1	1
847	1	1
848	1	1
849	1	1
850	1	1
851	1	1
			MISSING_ELSE
861	1	1
862	1	1
863	1	1

---

Cond Coverage for Instance : tb.dut.u_app_intf

	Total	Covered	Percent
Conditions	57	51	89.47
Logical	57	51	89.47
Non-Logical	0	0
Event	0	0

 LINE       309
 EXPRESSION (i == app_id)
            ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       310
 EXPRESSION (app_data_ready | fsm_data_ready)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T11
1	0	Covered	T12,T13,T6

 LINE       310
 EXPRESSION (app_digest_done | fsm_digest_done_q)
             -------1-------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T21,T22
1	0	Covered	T12,T13,T6

 LINE       310
 EXPRESSION (error_i | fsm_digest_done_q | sparse_fsm_error_o | service_rejected_error)
             ---1---   --------2--------   ---------3--------   -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T21,T23,T24
0	0	1	0	Covered	T25,T26,T27
0	1	0	0	Covered	T20,T22,T28
1	0	0	0	Covered	T7,T8,T29

 LINE       429
 EXPRESSION (sw_cmd_i == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       450
 EXPRESSION ((kmac_pkg::AppCfg[app_id].Mode == AppKMAC) && ((!keymgr_key_i.valid)))
             ---------------------1--------------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T6
1	0	Covered	T12,T13,T6
1	1	Covered	T1,T2,T11

 LINE       450
 SUB-EXPRESSION (kmac_pkg::AppCfg[app_id].Mode == AppKMAC)
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T12,T13,T6
1	Covered	T1,T2,T11

 LINE       468
 EXPRESSION (app_i[app_id].valid && app_o[app_id].ready && app_i[app_id].last)
             ---------1---------    ---------2---------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T30,T31,T32
1	1	0	Covered	T12,T13,T6
1	1	1	Covered	T12,T13,T6

 LINE       469
 EXPRESSION (kmac_pkg::AppCfg[app_id].Mode == AppKMAC)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T12,T13,T6
1	Covered	T12,T13,T6

 LINE       482
 EXPRESSION (kmac_valid_o && kmac_ready_i)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable	T7,T8,T30
1	1	Covered	T12,T13,T6

 LINE       512
 EXPRESSION (sw_cmd_i == CmdDone)
            ----------1----------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       542
 EXPRESSION (app_i[app_id].valid && app_i[app_id].last)
             ---------1---------    ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T11
1	1	Covered	T20,T21,T22

 LINE       650
 EXPRESSION ((mux_sel_buf_err_check != SelSw) && sw_valid_i)
             ----------------1---------------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T33,T34,T25

 LINE       650
 SUB-EXPRESSION (mux_sel_buf_err_check != SelSw)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       657
 EXPRESSION (app_active_o && (sw_cmd_i != CmdNone))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T11
1	1	Covered	T34,T35,T36

 LINE       657
 SUB-EXPRESSION (sw_cmd_i != CmdNone)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       811
 EXPRESSION (app_id == i)
            ------1------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T1,T2,T11

 LINE       812
 EXPRESSION (kmac_pkg::AppCfg[i].PrefixMode == 1'b0)
            --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Not Covered

 LINE       844
 EXPRESSION ((kmac_pkg::AppCfg[arb_idx].Mode == AppKMAC) ? 1'b1 : 1'b0)
             ---------------------1---------------------

-1-	Status	Tests
0	Covered	T12,T13,T6
1	Covered	T1,T2,T11

 LINE       844
 SUB-EXPRESSION (kmac_pkg::AppCfg[arb_idx].Mode == AppKMAC)
                ---------------------1---------------------

-1-	Status	Tests
0	Covered	T12,T13,T6
1	Covered	T1,T2,T11

 LINE       845
 EXPRESSION ((kmac_pkg::AppCfg[arb_idx].Mode == AppSHA3) ? Sha3 : CShake)
             ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Not Covered

 LINE       845
 SUB-EXPRESSION (kmac_pkg::AppCfg[arb_idx].Mode == AppSHA3)
                ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Not Covered

 LINE       848
 EXPRESSION (st == StIdle)
            -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_app_intf

Summary for FSM :: st

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	18	18	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAppCfg	425	Covered	T1,T2,T11
StAppMsg	459	Covered	T12,T13,T6
StAppOutLen	470	Covered	T12,T13,T6
StAppProcess	472	Covered	T12,T13,T6
StAppWait	491	Covered	T12,T13,T6
StError	446	Covered	T1,T2,T11
StIdle	434	Covered	T1,T2,T3
StKeyMgrErrKeyNotValid	452	Covered	T1,T2,T11
StServiceRejectedError	550	Covered	T21,T23,T24
StSw	430	Covered	T3,T4,T5
StTerminalError	584	Covered	T25,T26,T27

transitions	Line No.	Covered	Tests	Exclude Annotation
StAppCfg->StAppMsg	459	Covered	T12,T13,T6
StAppCfg->StError	446	Covered	T21,T23,T24
StAppCfg->StKeyMgrErrKeyNotValid	452	Covered	T1,T2,T11
StAppCfg->StTerminalError	584	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StAppMsg->StAppOutLen	470	Covered	T12,T13,T6
StAppMsg->StAppProcess	472	Covered	T12,T13,T6
StAppMsg->StTerminalError	584	Covered	T25,T37,T38
StAppOutLen->StAppProcess	483	Covered	T12,T13,T6
StAppOutLen->StTerminalError	584	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StAppProcess->StAppWait	491	Covered	T12,T13,T6
StAppProcess->StTerminalError	584	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StAppWait->StIdle	497	Covered	T12,T13,T6
StAppWait->StTerminalError	584	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StError->StIdle	536	Covered	T1,T2,T11
StError->StServiceRejectedError	550	Covered	T21,T23,T24
StError->StTerminalError	584	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StIdle->StAppCfg	425	Covered	T1,T2,T11
StIdle->StSw	430	Covered	T3,T4,T5
StIdle->StTerminalError	584	Covered	T39,T15,T16
StKeyMgrErrKeyNotValid->StError	520	Covered	T1,T2,T11
StKeyMgrErrKeyNotValid->StTerminalError	584	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StServiceRejectedError->StIdle	559	Covered	T21,T23,T24
StServiceRejectedError->StTerminalError	584	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StSw->StIdle	513	Covered	T3,T4,T5
StSw->StTerminalError	584	Covered	T26,T27,T40

---

Branch Coverage for Instance : tb.dut.u_app_intf

	Line No.	Total	Covered	Percent
Branches		71	70	98.59
IF	294	4	4	100.00
IF	309	2	2	100.00
IF	333	4	4	100.00
IF	380	2	2	100.00
IF	389	2	2	100.00
CASE	422	25	25	100.00
IF	583	2	2	100.00
CASE	611	4	4	100.00
IF	650	3	3	100.00
IF	714	3	3	100.00
IF	739	2	2	100.00
CASE	780	4	4	100.00
CASE	807	3	3	100.00
IF	834	8	7	87.50
CASE	861	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_app.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_app.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	294	if ((!rst_ni))
-2-:	295	if (service_rejected_error_set)
-3-:	296	if (service_rejected_error_clr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T21,T23,T24
0	0	1	Covered	T21,T23,T24
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	309	if ((i == app_id))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	333	if ((!rst_ni))
-2-:	334	if (clr_appid)
-3-:	335	if (set_appid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T11
0	0	1	Covered	T1,T2,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	380	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	389	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	422	case (st)
-2-:	424	if (arb_valid)
-3-:	429	if ((sw_cmd_i == CmdStart))
-4-:	439	if (((kmac_pkg::AppCfg[app_id].Mode == AppKMAC) && prim_mubi_pkg::mubi4_test_false_strict(entropy_ready_i)))
-5-:	450	if (((kmac_pkg::AppCfg[app_id].Mode == AppKMAC) && (!keymgr_key_i.valid)))
-6-:	468	if (((app_i[app_id].valid && app_o[app_id].ready) && app_i[app_id].last))
-7-:	469	if ((kmac_pkg::AppCfg[app_id].Mode == AppKMAC))
-8-:	482	if ((kmac_valid_o && kmac_ready_i))
-9-:	495	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_i))
-10-:	512	if ((sw_cmd_i == CmdDone))
-11-:	535	if (err_processed_i)
-12-:	542	if ((app_i[app_id].valid && app_i[app_id].last))
-13-:	546	if (service_rejected_error)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
StIdle	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StAppCfg	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T21,T23,T24
StAppCfg	-	-	0	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
StAppCfg	-	-	0	0	-	-	-	-	-	-	-	-	Covered	T12,T13,T6
StAppMsg	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T12,T13,T6
StAppMsg	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T12,T13,T6
StAppMsg	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T12,T13,T6
StAppOutLen	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T12,T13,T6
StAppOutLen	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T7,T8,T30
StAppProcess	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T6
StAppWait	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T12,T13,T6
StAppWait	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T12,T13,T6
StSw	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T3,T4,T5
StSw	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T3,T4,T5
StKeyMgrErrKeyNotValid	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
StError	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T2,T11
StError	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T11
StError	-	-	-	-	-	-	-	-	-	-	1	1	Covered	T21,T23,T24
StError	-	-	-	-	-	-	-	-	-	-	1	0	Covered	T20,T22,T28
StError	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T11
StServiceRejectedError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T23,T24
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T26,T27
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	583	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T25,T26,T27
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	611	case (mux_sel_buf_kmac)

Branches:

-1-	Status	Tests
SelApp	Covered	T12,T13,T6
SelOutLen	Covered	T12,T13,T6
SelSw	Covered	T3,T4,T5
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	650	if (((mux_sel_buf_err_check != SelSw) && sw_valid_i))
-2-:	657	if ((app_active_o && (sw_cmd_i != CmdNone)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T33,T34,T25
0	1	Covered	T34,T35,T36
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	714	if (((mux_sel_buf_output == SelSw) && lc_ctrl_pkg::lc_tx_test_false_strict(lc_escalate_en_i)))
-2-:	720	if (keymgr_key_en_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T12,T13,T6
1	0	Covered	T3,T4,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	739	if ((((st == StAppWait) && prim_mubi_pkg::mubi4_test_true_strict(absorbed_i)) && lc_ctrl_pkg::lc_tx_test_false_strict(lc_escalate_en_i)))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	780	case (st)
-2-:	789	if (keymgr_key_en_i)

Branches:

-1-	-2-	Status	Tests
StAppCfg StAppMsg StAppOutLen StAppProcess StAppWait	-	Covered	T1,T2,T11
StSw	1	Covered	T12,T13,T6
StSw	0	Covered	T3,T4,T5
default	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	807	case (st)

Branches:

-1-	Status	Tests
StAppCfg StAppMsg StAppOutLen StAppProcess StAppWait	Covered	T1,T2,T11
StSw	Covered	T3,T4,T5
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	834	if ((!rst_ni))
-2-:	838	if (clr_appid)
-3-:	843	if (set_appid)
-4-:	844	((kmac_pkg::AppCfg[arb_idx].Mode == AppKMAC)) ? 
-5-:	845	((kmac_pkg::AppCfg[arb_idx].Mode == AppSHA3)) ? 
-6-:	848	if ((st == StIdle))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T2,T11
0	0	1	1	-	-	Covered	T1,T2,T11
0	0	1	0	-	-	Covered	T12,T13,T6
0	0	1	-	1	-	Not Covered
0	0	1	-	0	-	Covered	T1,T2,T11
0	0	0	-	-	1	Covered	T1,T2,T3
0	0	0	-	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	861	case ({fsm_err.valid, mux_err.valid})

Branches:

-1-	Status	Tests
2'bz1	Covered	T33,T34,T25
2'b10	Covered	T1,T2,T11
default	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_app_intf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	1	1	100.00	1	100.00
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AppIntfInRange_A	1032	1032	0	0
SideloadKeySameToDigest_A	1032	1032	0	0
u_state_regs_A	2147483647	2147483647	0	0

AppIntfInRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032	1032	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

SideloadKeySameToDigest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032	1032	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	104658	104573	0	0
T2	74923	74838	0	0
T3	477575	477567	0	0
T4	21127	21028	0	0
T5	108477	108377	0	0
T10	1377	1305	0	0
T11	76447	76372	0	0
T12	122725	122718	0	0
T13	970460	970365	0	0
T14	204197	204190	0	0

---

Cover Directives for Properties: Details

Name	Attempts	Matches	Incomplete
AppIntfUseDifferentSizeKey_C	2147483647	2560	0

AppIntfUseDifferentSizeKey_C

Name	Attempts	Matches	Incomplete
Total	2147483647	2560	0
T1	104658	10	0
T2	74923	11	0
T3	477575	0	0
T4	21127	0	0
T5	108477	0	0
T6	0	12	0
T7	0	21	0
T8	0	6	0
T10	1377	0	0
T11	76447	11	0
T12	122725	15	0
T13	970460	12	0
T14	204197	0	0
T33	0	1	0
T41	0	11	0