Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1081694	0	0
entropy_period_rd_A	2147483647	1616	0	0
intr_enable_rd_A	2147483647	2213	0	0
prefix_0_rd_A	2147483647	1447	0	0
prefix_10_rd_A	2147483647	1521	0	0
prefix_1_rd_A	2147483647	1403	0	0
prefix_2_rd_A	2147483647	1474	0	0
prefix_3_rd_A	2147483647	1558	0	0
prefix_4_rd_A	2147483647	1447	0	0
prefix_5_rd_A	2147483647	1483	0	0
prefix_6_rd_A	2147483647	1505	0	0
prefix_7_rd_A	2147483647	1445	0	0
prefix_8_rd_A	2147483647	1329	0	0
prefix_9_rd_A	2147483647	1530	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1081694	0	0
T8	580921	86077	0	0
T19	218689	0	0	0
T20	57086	0	0	0
T33	138629	0	0	0
T41	596732	0	0	0
T53	705782	0	0	0
T60	0	26773	0	0
T64	6832	0	0	0
T65	103388	0	0	0
T66	868400	0	0	0
T67	195972	0	0	0
T82	0	19511	0	0
T83	0	59055	0	0
T135	0	18096	0	0
T136	0	114568	0	0
T137	0	126640	0	0
T138	0	22881	0	0
T139	0	149101	0	0
T140	0	17092	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1616	0	0
T82	596025	64	0	0
T83	0	97	0	0
T84	0	69	0	0
T91	0	41	0	0
T92	0	17	0	0
T153	0	3	0	0
T154	0	8	0	0
T155	0	31	0	0
T156	0	9	0	0
T157	0	11	0	0
T158	132253	0	0	0
T159	26391	0	0	0
T160	177672	0	0	0
T161	12131	0	0	0
T162	443358	0	0	0
T163	614754	0	0	0
T164	213890	0	0	0
T165	622349	0	0	0
T166	422306	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2213	0	0
T82	596025	51	0	0
T83	0	56	0	0
T84	0	54	0	0
T91	0	49	0	0
T92	0	8	0	0
T131	0	9	0	0
T153	0	20	0	0
T154	0	57	0	0
T155	0	56	0	0
T158	132253	0	0	0
T159	26391	0	0	0
T160	177672	0	0	0
T161	12131	0	0	0
T162	443358	0	0	0
T163	614754	0	0	0
T164	213890	0	0	0
T165	622349	0	0	0
T166	422306	0	0	0
T167	0	18	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1447	0	0
T82	596025	61	0	0
T83	0	88	0	0
T84	0	44	0	0
T91	0	28	0	0
T92	0	16	0	0
T153	0	4	0	0
T154	0	40	0	0
T155	0	25	0	0
T156	0	5	0	0
T157	0	6	0	0
T158	132253	0	0	0
T159	26391	0	0	0
T160	177672	0	0	0
T161	12131	0	0	0
T162	443358	0	0	0
T163	614754	0	0	0
T164	213890	0	0	0
T165	622349	0	0	0
T166	422306	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1521	0	0
T82	596025	48	0	0
T83	0	81	0	0
T84	0	50	0	0
T91	0	35	0	0
T92	0	14	0	0
T153	0	1	0	0
T154	0	51	0	0
T155	0	71	0	0
T156	0	12	0	0
T157	0	14	0	0
T158	132253	0	0	0
T159	26391	0	0	0
T160	177672	0	0	0
T161	12131	0	0	0
T162	443358	0	0	0
T163	614754	0	0	0
T164	213890	0	0	0
T165	622349	0	0	0
T166	422306	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1403	0	0
T82	596025	52	0	0
T83	0	86	0	0
T84	0	59	0	0
T91	0	29	0	0
T92	0	20	0	0
T153	0	5	0	0
T154	0	55	0	0
T155	0	51	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	132253	0	0	0
T159	26391	0	0	0
T160	177672	0	0	0
T161	12131	0	0	0
T162	443358	0	0	0
T163	614754	0	0	0
T164	213890	0	0	0
T165	622349	0	0	0
T166	422306	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1474	0	0
T82	596025	102	0	0
T83	0	84	0	0
T84	0	51	0	0
T91	0	23	0	0
T92	0	21	0	0
T153	0	14	0	0
T154	0	50	0	0
T155	0	52	0	0
T156	0	12	0	0
T157	0	20	0	0
T158	132253	0	0	0
T159	26391	0	0	0
T160	177672	0	0	0
T161	12131	0	0	0
T162	443358	0	0	0
T163	614754	0	0	0
T164	213890	0	0	0
T165	622349	0	0	0
T166	422306	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1558	0	0
T82	596025	49	0	0
T83	0	76	0	0
T84	0	71	0	0
T91	0	42	0	0
T92	0	16	0	0
T153	0	11	0	0
T154	0	42	0	0
T155	0	41	0	0
T156	0	12	0	0
T157	0	7	0	0
T158	132253	0	0	0
T159	26391	0	0	0
T160	177672	0	0	0
T161	12131	0	0	0
T162	443358	0	0	0
T163	614754	0	0	0
T164	213890	0	0	0
T165	622349	0	0	0
T166	422306	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1447	0	0
T82	596025	61	0	0
T83	0	80	0	0
T84	0	59	0	0
T91	0	17	0	0
T92	0	14	0	0
T153	0	9	0	0
T154	0	43	0	0
T155	0	51	0	0
T156	0	12	0	0
T157	0	8	0	0
T158	132253	0	0	0
T159	26391	0	0	0
T160	177672	0	0	0
T161	12131	0	0	0
T162	443358	0	0	0
T163	614754	0	0	0
T164	213890	0	0	0
T165	622349	0	0	0
T166	422306	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1483	0	0
T82	596025	56	0	0
T83	0	87	0	0
T84	0	95	0	0
T91	0	36	0	0
T92	0	3	0	0
T153	0	12	0	0
T154	0	44	0	0
T155	0	64	0	0
T156	0	8	0	0
T157	0	8	0	0
T158	132253	0	0	0
T159	26391	0	0	0
T160	177672	0	0	0
T161	12131	0	0	0
T162	443358	0	0	0
T163	614754	0	0	0
T164	213890	0	0	0
T165	622349	0	0	0
T166	422306	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1505	0	0
T82	596025	69	0	0
T83	0	67	0	0
T84	0	45	0	0
T91	0	27	0	0
T92	0	17	0	0
T153	0	9	0	0
T154	0	28	0	0
T155	0	43	0	0
T156	0	6	0	0
T157	0	12	0	0
T158	132253	0	0	0
T159	26391	0	0	0
T160	177672	0	0	0
T161	12131	0	0	0
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T163	614754	0	0	0
T164	213890	0	0	0
T165	622349	0	0	0
T166	422306	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1445	0	0
T82	596025	62	0	0
T83	0	57	0	0
T84	0	68	0	0
T91	0	22	0	0
T92	0	8	0	0
T153	0	13	0	0
T154	0	44	0	0
T155	0	56	0	0
T156	0	7	0	0
T157	0	5	0	0
T158	132253	0	0	0
T159	26391	0	0	0
T160	177672	0	0	0
T161	12131	0	0	0
T162	443358	0	0	0
T163	614754	0	0	0
T164	213890	0	0	0
T165	622349	0	0	0
T166	422306	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1329	0	0
T82	596025	47	0	0
T83	0	62	0	0
T84	0	49	0	0
T91	0	33	0	0
T92	0	16	0	0
T153	0	8	0	0
T154	0	25	0	0
T155	0	3	0	0
T156	0	5	0	0
T157	0	11	0	0
T158	132253	0	0	0
T159	26391	0	0	0
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T163	614754	0	0	0
T164	213890	0	0	0
T165	622349	0	0	0
T166	422306	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1530	0	0
T82	596025	62	0	0
T83	0	56	0	0
T84	0	65	0	0
T91	0	36	0	0
T92	0	21	0	0
T153	0	3	0	0
T154	0	68	0	0
T155	0	22	0	0
T156	0	5	0	0
T157	0	5	0	0
T158	132253	0	0	0
T159	26391	0	0	0
T160	177672	0	0	0
T161	12131	0	0	0
T162	443358	0	0	0
T163	614754	0	0	0
T164	213890	0	0	0
T165	622349	0	0	0
T166	422306	0	0	0