Design subhierarchy
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NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
 gen_entropy.u_entropy 97.83 100.00 87.97 100.00 100.00 98.98 100.00
 gen_entropy.u_prim_sync_reqack_data 95.83 100.00 83.33 100.00 100.00
intr_fifo_empty 86.94 90.00 77.78 80.00 100.00
intr_kmac_done 93.75 100.00 75.00 100.00 100.00
intr_kmac_err 93.75 100.00 75.00 100.00 100.00
kmac_csr_assert 100.00 100.00
sha3pad_assert_cov_if 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
 u_app_intf 83.87 94.07 88.60 44.44 92.23 100.00
 u_errchk 92.66 95.18 94.59 80.00 93.55 100.00
 u_kmac_core 95.80 98.88 92.86 100.00 100.00 91.38 91.67
 u_msgfifo 97.43 100.00 95.83 94.52 100.00 94.23 100.00
 u_prim_lc_sync 100.00 100.00 100.00 100.00
 u_reg 98.99 99.25 96.97 100.00 98.72 100.00
 u_sha3 96.98 98.85 95.87 100.00 90.48 96.71 100.00
 u_sha3_done_sender 100.00 100.00 100.00 100.00
 u_state_regs 100.00 100.00 100.00 100.00
 u_staterd 89.95 89.88 81.39 88.54 100.00
 u_tlul_adapter_msgfifo 79.91 87.01 74.59 77.38 80.65