Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	469781	0	0
entropy_period_rd_A	2147483647	1472	0	0
intr_enable_rd_A	2147483647	2004	0	0
prefix_0_rd_A	2147483647	1275	0	0
prefix_10_rd_A	2147483647	1381	0	0
prefix_1_rd_A	2147483647	1409	0	0
prefix_2_rd_A	2147483647	1343	0	0
prefix_3_rd_A	2147483647	1325	0	0
prefix_4_rd_A	2147483647	1345	0	0
prefix_5_rd_A	2147483647	1311	0	0
prefix_6_rd_A	2147483647	1223	0	0
prefix_7_rd_A	2147483647	1304	0	0
prefix_8_rd_A	2147483647	1408	0	0
prefix_9_rd_A	2147483647	1250	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	469781	0	0
T2	277887	35592	0	0
T3	116064	0	0	0
T7	179519	0	0	0
T17	130686	0	0	0
T18	288395	0	0	0
T20	0	111314	0	0
T21	0	19057	0	0
T29	775405	0	0	0
T30	177885	0	0	0
T31	150651	0	0	0
T32	150554	0	0	0
T33	109437	0	0	0
T54	0	53559	0	0
T68	0	25729	0	0
T69	0	10081	0	0
T117	0	34666	0	0
T118	0	72878	0	0
T119	0	27747	0	0
T120	0	76354	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1472	0	0
T54	103293	152	0	0
T68	0	25	0	0
T69	0	26	0	0
T78	0	4	0	0
T79	0	6	0	0
T127	0	14	0	0
T128	0	1	0	0
T129	0	45	0	0
T130	0	4	0	0
T131	0	10	0	0
T132	332597	0	0	0
T133	301864	0	0	0
T134	102669	0	0	0
T135	931576	0	0	0
T136	123970	0	0	0
T137	814996	0	0	0
T138	972512	0	0	0
T139	86024	0	0	0
T140	571385	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2004	0	0
T54	103293	116	0	0
T68	0	36	0	0
T69	0	42	0	0
T78	0	1	0	0
T79	0	5	0	0
T81	0	3	0	0
T127	0	18	0	0
T129	0	61	0	0
T132	332597	0	0	0
T133	301864	0	0	0
T134	102669	0	0	0
T135	931576	0	0	0
T136	123970	0	0	0
T137	814996	0	0	0
T138	972512	0	0	0
T139	86024	0	0	0
T140	571385	0	0	0
T141	0	2	0	0
T142	0	6	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1275	0	0
T54	103293	86	0	0
T68	0	18	0	0
T69	0	27	0	0
T78	0	9	0	0
T79	0	4	0	0
T81	0	3	0	0
T127	0	11	0	0
T128	0	6	0	0
T129	0	56	0	0
T131	0	4	0	0
T132	332597	0	0	0
T133	301864	0	0	0
T134	102669	0	0	0
T135	931576	0	0	0
T136	123970	0	0	0
T137	814996	0	0	0
T138	972512	0	0	0
T139	86024	0	0	0
T140	571385	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1381	0	0
T54	103293	171	0	0
T68	0	42	0	0
T69	0	48	0	0
T78	0	1	0	0
T79	0	9	0	0
T127	0	1	0	0
T128	0	2	0	0
T129	0	58	0	0
T130	0	4	0	0
T132	332597	0	0	0
T133	301864	0	0	0
T134	102669	0	0	0
T135	931576	0	0	0
T136	123970	0	0	0
T137	814996	0	0	0
T138	972512	0	0	0
T139	86024	0	0	0
T140	571385	0	0	0
T141	0	1	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1409	0	0
T54	103293	115	0	0
T68	0	70	0	0
T69	0	65	0	0
T78	0	4	0	0
T79	0	10	0	0
T81	0	7	0	0
T127	0	8	0	0
T128	0	4	0	0
T129	0	68	0	0
T131	0	2	0	0
T132	332597	0	0	0
T133	301864	0	0	0
T134	102669	0	0	0
T135	931576	0	0	0
T136	123970	0	0	0
T137	814996	0	0	0
T138	972512	0	0	0
T139	86024	0	0	0
T140	571385	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1343	0	0
T54	103293	98	0	0
T68	0	51	0	0
T69	0	62	0	0
T78	0	6	0	0
T79	0	5	0	0
T81	0	6	0	0
T127	0	12	0	0
T128	0	4	0	0
T129	0	50	0	0
T132	332597	0	0	0
T133	301864	0	0	0
T134	102669	0	0	0
T135	931576	0	0	0
T136	123970	0	0	0
T137	814996	0	0	0
T138	972512	0	0	0
T139	86024	0	0	0
T140	571385	0	0	0
T141	0	3	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1325	0	0
T54	103293	169	0	0
T68	0	16	0	0
T69	0	23	0	0
T78	0	2	0	0
T79	0	2	0	0
T81	0	3	0	0
T127	0	1	0	0
T128	0	10	0	0
T129	0	54	0	0
T130	0	7	0	0
T132	332597	0	0	0
T133	301864	0	0	0
T134	102669	0	0	0
T135	931576	0	0	0
T136	123970	0	0	0
T137	814996	0	0	0
T138	972512	0	0	0
T139	86024	0	0	0
T140	571385	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1345	0	0
T54	103293	173	0	0
T68	0	58	0	0
T69	0	48	0	0
T78	0	2	0	0
T79	0	2	0	0
T81	0	5	0	0
T127	0	2	0	0
T128	0	5	0	0
T129	0	31	0	0
T130	0	9	0	0
T132	332597	0	0	0
T133	301864	0	0	0
T134	102669	0	0	0
T135	931576	0	0	0
T136	123970	0	0	0
T137	814996	0	0	0
T138	972512	0	0	0
T139	86024	0	0	0
T140	571385	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1311	0	0
T54	103293	131	0	0
T68	0	27	0	0
T69	0	49	0	0
T78	0	1	0	0
T81	0	5	0	0
T127	0	5	0	0
T128	0	6	0	0
T129	0	81	0	0
T130	0	7	0	0
T131	0	10	0	0
T132	332597	0	0	0
T133	301864	0	0	0
T134	102669	0	0	0
T135	931576	0	0	0
T136	123970	0	0	0
T137	814996	0	0	0
T138	972512	0	0	0
T139	86024	0	0	0
T140	571385	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1223	0	0
T54	103293	76	0	0
T68	0	42	0	0
T69	0	46	0	0
T78	0	7	0	0
T127	0	9	0	0
T128	0	7	0	0
T129	0	14	0	0
T130	0	7	0	0
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T134	102669	0	0	0
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T139	86024	0	0	0
T140	571385	0	0	0
T141	0	3	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1304	0	0
T54	103293	121	0	0
T68	0	55	0	0
T69	0	46	0	0
T78	0	6	0	0
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T81	0	3	0	0
T127	0	2	0	0
T129	0	57	0	0
T130	0	1	0	0
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T132	332597	0	0	0
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T138	972512	0	0	0
T139	86024	0	0	0
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prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1408	0	0
T54	103293	142	0	0
T68	0	59	0	0
T69	0	56	0	0
T78	0	8	0	0
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T128	0	2	0	0
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T136	123970	0	0	0
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T139	86024	0	0	0
T140	571385	0	0	0
T141	0	5	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1250	0	0
T54	103293	139	0	0
T68	0	53	0	0
T69	0	40	0	0
T79	0	2	0	0
T81	0	5	0	0
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