Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170256 |
1 |
|
|
T3 |
916 |
|
T7 |
1080 |
|
T8 |
103 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
87712 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
61729 |
1 |
|
|
T3 |
904 |
|
T7 |
34 |
|
T8 |
102 |
seven_bytes |
2977 |
1 |
|
|
T7 |
34 |
|
T16 |
46 |
|
T17 |
58 |
six_bytes |
3030 |
1 |
|
|
T7 |
29 |
|
T16 |
47 |
|
T17 |
62 |
five_bytes |
3024 |
1 |
|
|
T7 |
30 |
|
T16 |
47 |
|
T17 |
54 |
four_bytes |
2916 |
1 |
|
|
T7 |
32 |
|
T16 |
35 |
|
T17 |
56 |
three_bytes |
2921 |
1 |
|
|
T7 |
34 |
|
T16 |
48 |
|
T17 |
71 |
two_bytes |
3011 |
1 |
|
|
T7 |
27 |
|
T16 |
36 |
|
T17 |
69 |
one_byte |
2936 |
1 |
|
|
T7 |
40 |
|
T16 |
42 |
|
T17 |
69 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167030 |
1 |
|
|
T3 |
892 |
|
T7 |
1064 |
|
T8 |
101 |
auto[1] |
3226 |
1 |
|
|
T3 |
24 |
|
T7 |
16 |
|
T8 |
2 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170256 |
1 |
|
|
T3 |
916 |
|
T7 |
1080 |
|
T8 |
103 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170244 |
1 |
|
|
T3 |
916 |
|
T7 |
1080 |
|
T8 |
103 |
auto[1] |
12 |
1 |
|
|
T14 |
1 |
|
T10 |
2 |
|
T183 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1155 |
1 |
|
|
T3 |
12 |
|
T7 |
2 |
|
T8 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3226 |
1 |
|
|
T3 |
24 |
|
T7 |
16 |
|
T8 |
2 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
165287 |
1 |
|
|
T3 |
701 |
|
T7 |
802 |
|
T9 |
220 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
84999 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
59996 |
1 |
|
|
T3 |
692 |
|
T7 |
22 |
|
T9 |
218 |
seven_bytes |
2874 |
1 |
|
|
T7 |
24 |
|
T16 |
41 |
|
T17 |
49 |
six_bytes |
2900 |
1 |
|
|
T7 |
18 |
|
T16 |
41 |
|
T17 |
45 |
five_bytes |
2902 |
1 |
|
|
T7 |
24 |
|
T16 |
32 |
|
T17 |
45 |
four_bytes |
2906 |
1 |
|
|
T7 |
18 |
|
T16 |
34 |
|
T17 |
63 |
three_bytes |
2864 |
1 |
|
|
T7 |
26 |
|
T16 |
30 |
|
T17 |
54 |
two_bytes |
2913 |
1 |
|
|
T7 |
27 |
|
T16 |
36 |
|
T17 |
44 |
one_byte |
2933 |
1 |
|
|
T7 |
27 |
|
T16 |
34 |
|
T17 |
41 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
162119 |
1 |
|
|
T3 |
683 |
|
T7 |
792 |
|
T9 |
216 |
auto[1] |
3168 |
1 |
|
|
T3 |
18 |
|
T7 |
10 |
|
T9 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
165287 |
1 |
|
|
T3 |
701 |
|
T7 |
802 |
|
T9 |
220 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
165274 |
1 |
|
|
T3 |
701 |
|
T7 |
802 |
|
T9 |
220 |
auto[1] |
13 |
1 |
|
|
T184 |
1 |
|
T11 |
1 |
|
T144 |
2 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1110 |
1 |
|
|
T3 |
9 |
|
T7 |
3 |
|
T9 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3168 |
1 |
|
|
T3 |
18 |
|
T7 |
10 |
|
T9 |
4 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
326792 |
1 |
|
|
T2 |
2 |
|
T3 |
896 |
|
T7 |
4267 |
auto[1] |
519 |
1 |
|
|
T9 |
6 |
|
T10 |
42 |
|
T11 |
81 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
166503 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
121176 |
1 |
|
|
T2 |
2 |
|
T3 |
884 |
|
T7 |
104 |
seven_bytes |
5711 |
1 |
|
|
T7 |
107 |
|
T16 |
117 |
|
T17 |
93 |
six_bytes |
5766 |
1 |
|
|
T7 |
129 |
|
T16 |
110 |
|
T17 |
87 |
five_bytes |
5700 |
1 |
|
|
T7 |
124 |
|
T16 |
109 |
|
T17 |
112 |
four_bytes |
5609 |
1 |
|
|
T7 |
112 |
|
T16 |
134 |
|
T17 |
97 |
three_bytes |
5616 |
1 |
|
|
T7 |
117 |
|
T16 |
128 |
|
T17 |
95 |
two_bytes |
5607 |
1 |
|
|
T7 |
120 |
|
T16 |
118 |
|
T17 |
96 |
one_byte |
5623 |
1 |
|
|
T7 |
134 |
|
T16 |
117 |
|
T17 |
117 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
320909 |
1 |
|
|
T2 |
2 |
|
T3 |
872 |
|
T7 |
4211 |
auto[1] |
6402 |
1 |
|
|
T3 |
24 |
|
T7 |
56 |
|
T9 |
12 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
327311 |
1 |
|
|
T2 |
2 |
|
T3 |
896 |
|
T7 |
4267 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
327282 |
1 |
|
|
T2 |
2 |
|
T3 |
896 |
|
T7 |
4267 |
auto[1] |
29 |
1 |
|
|
T10 |
2 |
|
T185 |
1 |
|
T186 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2228 |
1 |
|
|
T3 |
12 |
|
T7 |
8 |
|
T9 |
6 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6402 |
1 |
|
|
T3 |
24 |
|
T7 |
56 |
|
T9 |
12 |