Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 257973003 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 183512415 1 T1 156 T2 160 T3 35693



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 228458057 1 T1 80 T2 74 T3 46486
values[0x0] 102397328 1 T1 52 T2 49 T3 8450
values[0x1] 110630033 1 T1 48 T2 49 T3 8946



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 200612463 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 240872955 1 T1 165 T2 163 T3 43087



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 1697304 1 T2 1 T3 9 T15 4334
valid_sources[0x01] 3707315 1 T2 1 T3 19 T15 4429
valid_sources[0x02] 1376724 1 T2 1 T3 9 T15 4199
valid_sources[0x03] 3443909 1 T3 17 T15 4296 T18 2461
valid_sources[0x04] 1376927 1 T1 3 T3 9 T15 4453
valid_sources[0x05] 2285583 1 T1 1 T3 21 T15 4312
valid_sources[0x06] 1453046 1 T1 1 T2 2 T3 6
valid_sources[0x07] 2282853 1 T2 1 T3 17 T15 4279
valid_sources[0x08] 1825243 1 T3 18 T15 4319 T18 2572
valid_sources[0x09] 1380253 1 T2 1 T3 19 T15 5076
valid_sources[0x0a] 1377758 1 T3 11 T15 4537 T18 2463
valid_sources[0x0b] 1381830 1 T2 1 T3 12 T15 4569
valid_sources[0x0c] 1746519 1 T1 3 T3 11 T15 4187
valid_sources[0x0d] 1376410 1 T2 2 T3 16 T15 4598
valid_sources[0x0e] 1379905 1 T1 4 T2 1 T3 11
valid_sources[0x0f] 1504339 1 T3 19 T15 4160 T18 2509
valid_sources[0x10] 1427192 1 T2 1 T3 10 T15 4549
valid_sources[0x11] 1379556 1 T1 1 T3 19 T15 4616
valid_sources[0x12] 2235821 1 T3 12 T15 4448 T18 2473
valid_sources[0x13] 1375097 1 T2 3 T3 16 T15 4778
valid_sources[0x14] 2208507 1 T3 19 T15 4565 T18 2492
valid_sources[0x15] 1375910 1 T1 2 T2 2 T3 17
valid_sources[0x16] 1369235 1 T3 20 T15 4457 T18 2486
valid_sources[0x17] 1393385 1 T3 13 T15 4340 T18 2499
valid_sources[0x18] 1374896 1 T2 1 T3 15 T15 4442
valid_sources[0x19] 1380672 1 T1 1 T2 1 T3 14
valid_sources[0x1a] 1373432 1 T2 1 T3 18 T15 4490
valid_sources[0x1b] 1388974 1 T2 1 T3 15 T15 4305
valid_sources[0x1c] 1405390 1 T3 10 T15 4462 T18 2567
valid_sources[0x1d] 1379970 1 T1 6 T3 13 T15 4493
valid_sources[0x1e] 1372844 1 T3 16 T15 4680 T18 2516
valid_sources[0x1f] 1379668 1 T1 2 T2 1 T3 17
valid_sources[0x20] 1402930 1 T3 13 T15 4617 T18 2534
valid_sources[0x21] 1378600 1 T3 12 T15 4523 T18 2487
valid_sources[0x22] 1375727 1 T2 2 T3 15 T15 4465
valid_sources[0x23] 1375279 1 T3 7 T15 4628 T18 2460
valid_sources[0x24] 1392013 1 T3 15 T15 4946 T18 2491
valid_sources[0x25] 1380151 1 T3 17 T15 4552 T18 2558
valid_sources[0x26] 1385201 1 T1 3 T2 1 T3 11
valid_sources[0x27] 1541759 1 T1 1 T3 10 T15 4379
valid_sources[0x28] 3359839 1 T3 12 T15 4698 T18 2521
valid_sources[0x29] 1411233 1 T1 4 T2 1 T3 16
valid_sources[0x2a] 3671554 1 T2 2 T3 14 T15 4890
valid_sources[0x2b] 2479865 1 T1 1 T2 1 T3 8
valid_sources[0x2c] 1382062 1 T2 1 T3 21 T15 4588
valid_sources[0x2d] 1377143 1 T1 1 T2 2 T3 10
valid_sources[0x2e] 1372455 1 T1 4 T3 17 T15 4880
valid_sources[0x2f] 1830410 1 T1 1 T2 1 T3 13
valid_sources[0x30] 1375215 1 T1 2 T2 1 T3 13
valid_sources[0x31] 1376892 1 T2 2 T3 19 T15 4441
valid_sources[0x32] 1376485 1 T2 1 T3 15 T15 4875
valid_sources[0x33] 1477226 1 T2 1 T3 11 T15 4611
valid_sources[0x34] 1453947 1 T1 1 T3 14 T15 4464
valid_sources[0x35] 1396270 1 T1 1 T2 1 T3 14
valid_sources[0x36] 1528767 1 T3 14 T15 4165 T18 2392
valid_sources[0x37] 1376651 1 T3 10 T15 4909 T18 2572
valid_sources[0x38] 1375597 1 T1 1 T2 1 T3 16
valid_sources[0x39] 1665007 1 T2 1 T3 12 T15 4444
valid_sources[0x3a] 1376757 1 T2 1 T3 19 T15 4166
valid_sources[0x3b] 1376445 1 T2 2 T3 10 T15 4843
valid_sources[0x3c] 2280227 1 T1 1 T2 2 T3 14
valid_sources[0x3d] 2027440 1 T3 10 T15 4458 T18 2557
valid_sources[0x3e] 1506407 1 T3 18 T15 4363 T18 2564
valid_sources[0x3f] 1514900 1 T2 1 T3 9 T15 4666
valid_sources[0x40] 1391724 1 T3 14 T15 4140 T18 2432
valid_sources[0x41] 2314224 1 T2 2 T3 15 T15 4518
valid_sources[0x42] 1381408 1 T1 1 T2 1 T3 16
valid_sources[0x43] 1378220 1 T2 2 T3 18 T15 4902
valid_sources[0x44] 1380835 1 T1 1 T3 13 T15 4542
valid_sources[0x45] 1447365 1 T3 14 T15 4551 T18 2472
valid_sources[0x46] 1372643 1 T1 2 T3 9 T15 4382
valid_sources[0x47] 1393135 1 T1 1 T2 1 T3 12
valid_sources[0x48] 1740763 1 T2 2 T3 13 T15 4441
valid_sources[0x49] 1380993 1 T3 15 T15 4197 T18 2644
valid_sources[0x4a] 1376753 1 T3 11 T15 4459 T18 2531
valid_sources[0x4b] 1371563 1 T1 1 T3 15 T15 4206
valid_sources[0x4c] 1381350 1 T2 1 T3 14 T15 4618
valid_sources[0x4d] 3952912 1 T2 1 T3 20 T15 5074
valid_sources[0x4e] 1374106 1 T2 1 T3 11 T15 4290
valid_sources[0x4f] 1375487 1 T3 14 T15 4463 T18 2491
valid_sources[0x50] 1379819 1 T3 16 T15 4280 T18 2399
valid_sources[0x51] 1377498 1 T1 2 T3 20 T15 4394
valid_sources[0x52] 3709756 1 T2 1 T3 10 T15 4546
valid_sources[0x53] 1375039 1 T1 1 T2 1 T3 17
valid_sources[0x54] 1373595 1 T3 19 T15 4364 T18 2431
valid_sources[0x55] 1559576 1 T2 1 T3 11 T15 4455
valid_sources[0x56] 1379220 1 T3 14 T15 4268 T18 2446
valid_sources[0x57] 2827335 1 T1 2 T3 17 T15 4463
valid_sources[0x58] 3751501 1 T2 1 T3 11 T15 4659
valid_sources[0x59] 1385533 1 T2 1 T3 14 T15 4478
valid_sources[0x5a] 1370124 1 T1 1 T3 18 T15 4334
valid_sources[0x5b] 3795297 1 T3 10 T15 4301 T18 2518
valid_sources[0x5c] 1374616 1 T2 1 T3 16 T15 4319
valid_sources[0x5d] 1379913 1 T1 2 T2 1 T3 16
valid_sources[0x5e] 1375737 1 T2 2 T3 14 T15 4749
valid_sources[0x5f] 2027106 1 T1 2 T3 15 T15 4427
valid_sources[0x60] 1382347 1 T3 12 T15 4618 T18 2561
valid_sources[0x61] 1377549 1 T2 1 T3 13 T15 4546
valid_sources[0x62] 1374815 1 T1 2 T3 9 T15 4375
valid_sources[0x63] 1385396 1 T2 1 T3 13 T15 4367
valid_sources[0x64] 1379743 1 T2 1 T3 12 T15 4308
valid_sources[0x65] 1372416 1 T3 12 T15 4548 T18 2531
valid_sources[0x66] 1371085 1 T1 1 T2 2 T3 17
valid_sources[0x67] 1374952 1 T1 1 T2 1 T3 12
valid_sources[0x68] 2350168 1 T2 4 T3 60355 T15 4447
valid_sources[0x69] 1384051 1 T2 1 T3 12 T15 4197
valid_sources[0x6a] 1400732 1 T2 1 T3 9 T15 4385
valid_sources[0x6b] 1389253 1 T3 18 T15 4332 T18 2457
valid_sources[0x6c] 1379095 1 T3 16 T15 4598 T18 2602
valid_sources[0x6d] 1374201 1 T3 12 T15 4403 T18 2504
valid_sources[0x6e] 3346341 1 T1 1 T3 15 T15 4531
valid_sources[0x6f] 1385238 1 T2 2 T3 14 T15 4144
valid_sources[0x70] 1426215 1 T3 10 T15 4401 T18 2522
valid_sources[0x71] 1405130 1 T2 1 T3 11 T15 4283
valid_sources[0x72] 1378600 1 T1 4 T2 2 T3 13
valid_sources[0x73] 1372173 1 T1 5 T2 1 T3 7
valid_sources[0x74] 1381113 1 T3 15 T15 4604 T18 2517
valid_sources[0x75] 1376310 1 T3 11 T15 4785 T18 2486
valid_sources[0x76] 2042886 1 T3 14 T15 4711 T18 2469
valid_sources[0x77] 1441081 1 T3 9 T15 4604 T18 2685
valid_sources[0x78] 1460713 1 T2 1 T3 19 T15 4687
valid_sources[0x79] 2205974 1 T2 1 T3 8 T15 4489
valid_sources[0x7a] 1391076 1 T3 13 T15 4130 T18 2570
valid_sources[0x7b] 1377919 1 T3 11 T15 4429 T18 2459
valid_sources[0x7c] 1375138 1 T2 1 T3 13 T15 4341
valid_sources[0x7d] 1494451 1 T2 1 T3 10 T15 4327
valid_sources[0x7e] 1379449 1 T1 4 T2 1 T3 10
valid_sources[0x7f] 3449363 1 T1 2 T3 11 T15 4739
valid_sources[0x80] 1391800 1 T3 10 T15 4678 T18 2604



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 70925157 1 T1 70 T2 69 T3 25324
values[0x0] all_enables biggest_size 60506344 1 T1 46 T2 46 T3 5483
values[0x1] all_enables biggest_size 52080914 1 T1 40 T2 45 T3 4886

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%