Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

259062039

1

T1

24

T2

12

T3

28189

full_word

183580937

1

T1

156

T2

160

T3

35693

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	442642656	1			T1	180		T2	172		T3	63882
auto[TlIntgErrCmd]	99	1			T130	6		T131	3		T132	3
auto[TlIntgErrData]	125	1			T130	9		T131	4		T132	6
auto[TlIntgErrBoth]	96	1			T130	5		T131	3		T132	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

228668880

1

T1

80

T2

74

T3

46486

auto[1]

213974096

1

T1

100

T2

98

T3

17396

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	157726465	1			T1	10		T2	5		T3	21162
auto[TlIntgErrNone]	partial	auto[1]	101335283	1			T1	14		T2	7		T3	7027
auto[TlIntgErrNone]	full_word	auto[0]	70942285	1			T1	70		T2	69		T3	25324
auto[TlIntgErrNone]	full_word	auto[1]	112638623	1			T1	86		T2	91		T3	10369
auto[TlIntgErrCmd]	partial	auto[0]	29	1			T130	2		T131	1		T132	2
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T130	4		T131	2		T132	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T179	1		T188	1		T189	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T180	1		T190	1		T188	1
auto[TlIntgErrData]	partial	auto[0]	57	1			T130	4		T131	2		T132	3
auto[TlIntgErrData]	partial	auto[1]	58	1			T130	4		T131	1		T132	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T130	1		T179	1		T191	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T131	1		T192	2		T188	2
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T130	2		T131	1		T179	2
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T130	2		T131	1		T179	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T131	1		T193	1		T182	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T130	1		T132	1		T179	2