Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	249928	0	0
entropy_period_rd_A	2147483647	1742	0	0
intr_enable_rd_A	2147483647	2189	0	0
prefix_0_rd_A	2147483647	1436	0	0
prefix_10_rd_A	2147483647	1534	0	0
prefix_1_rd_A	2147483647	1414	0	0
prefix_2_rd_A	2147483647	1430	0	0
prefix_3_rd_A	2147483647	1454	0	0
prefix_4_rd_A	2147483647	1381	0	0
prefix_5_rd_A	2147483647	1523	0	0
prefix_6_rd_A	2147483647	1337	0	0
prefix_7_rd_A	2147483647	1453	0	0
prefix_8_rd_A	2147483647	1529	0	0
prefix_9_rd_A	2147483647	1383	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	249928	0	0
T11	464020	0	0	0
T24	0	102186	0	0
T64	1421	0	0	0
T69	210708	15892	0	0
T70	0	47288	0	0
T137	0	17815	0	0
T138	0	63525	0	0
T139	0	23	0	0
T140	0	52	0	0
T141	0	74	0	0
T142	0	55	0	0
T143	0	6	0	0
T144	536427	0	0	0
T145	211447	0	0	0
T146	8503	0	0	0
T147	206303	0	0	0
T148	274104	0	0	0
T149	377246	0	0	0
T150	29340	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1742	0	0
T11	464020	0	0	0
T64	1421	0	0	0
T69	210708	70	0	0
T97	0	28	0	0
T98	0	35	0	0
T131	0	63	0	0
T132	0	84	0	0
T134	0	3	0	0
T144	536427	0	0	0
T145	211447	0	0	0
T146	8503	0	0	0
T147	206303	0	0	0
T148	274104	0	0	0
T149	377246	0	0	0
T150	29340	0	0	0
T151	0	12	0	0
T166	0	1	0	0
T167	0	10	0	0
T168	0	12	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2189	0	0
T11	464020	0	0	0
T64	1421	0	0	0
T69	210708	30	0	0
T97	0	35	0	0
T98	0	54	0	0
T131	0	80	0	0
T134	0	1	0	0
T135	0	6	0	0
T136	0	23	0	0
T144	536427	0	0	0
T145	211447	0	0	0
T146	8503	0	0	0
T147	206303	0	0	0
T148	274104	0	0	0
T149	377246	0	0	0
T150	29340	0	0	0
T151	0	3	0	0
T166	0	18	0	0
T167	0	9	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1436	0	0
T11	464020	0	0	0
T64	1421	0	0	0
T69	210708	62	0	0
T97	0	13	0	0
T98	0	18	0	0
T131	0	49	0	0
T132	0	48	0	0
T134	0	3	0	0
T144	536427	0	0	0
T145	211447	0	0	0
T146	8503	0	0	0
T147	206303	0	0	0
T148	274104	0	0	0
T149	377246	0	0	0
T150	29340	0	0	0
T151	0	4	0	0
T166	0	14	0	0
T167	0	29	0	0
T169	0	27	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1534	0	0
T11	464020	0	0	0
T64	1421	0	0	0
T69	210708	57	0	0
T97	0	10	0	0
T98	0	32	0	0
T131	0	52	0	0
T132	0	47	0	0
T134	0	5	0	0
T144	536427	0	0	0
T145	211447	0	0	0
T146	8503	0	0	0
T147	206303	0	0	0
T148	274104	0	0	0
T149	377246	0	0	0
T150	29340	0	0	0
T151	0	1	0	0
T166	0	26	0	0
T167	0	3	0	0
T169	0	67	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1414	0	0
T11	464020	0	0	0
T64	1421	0	0	0
T69	210708	42	0	0
T97	0	22	0	0
T98	0	14	0	0
T131	0	44	0	0
T132	0	38	0	0
T134	0	3	0	0
T144	536427	0	0	0
T145	211447	0	0	0
T146	8503	0	0	0
T147	206303	0	0	0
T148	274104	0	0	0
T149	377246	0	0	0
T150	29340	0	0	0
T151	0	1	0	0
T166	0	8	0	0
T167	0	21	0	0
T168	0	1	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1430	0	0
T11	464020	0	0	0
T64	1421	0	0	0
T69	210708	76	0	0
T97	0	19	0	0
T98	0	28	0	0
T131	0	36	0	0
T132	0	31	0	0
T134	0	2	0	0
T144	536427	0	0	0
T145	211447	0	0	0
T146	8503	0	0	0
T147	206303	0	0	0
T148	274104	0	0	0
T149	377246	0	0	0
T150	29340	0	0	0
T151	0	8	0	0
T166	0	23	0	0
T167	0	39	0	0
T168	0	8	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1454	0	0
T11	464020	0	0	0
T64	1421	0	0	0
T69	210708	77	0	0
T97	0	11	0	0
T98	0	32	0	0
T131	0	35	0	0
T132	0	42	0	0
T134	0	5	0	0
T144	536427	0	0	0
T145	211447	0	0	0
T146	8503	0	0	0
T147	206303	0	0	0
T148	274104	0	0	0
T149	377246	0	0	0
T150	29340	0	0	0
T151	0	6	0	0
T166	0	26	0	0
T167	0	52	0	0
T169	0	42	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1381	0	0
T11	464020	0	0	0
T64	1421	0	0	0
T69	210708	39	0	0
T97	0	15	0	0
T98	0	26	0	0
T131	0	53	0	0
T132	0	52	0	0
T134	0	5	0	0
T144	536427	0	0	0
T145	211447	0	0	0
T146	8503	0	0	0
T147	206303	0	0	0
T148	274104	0	0	0
T149	377246	0	0	0
T150	29340	0	0	0
T151	0	6	0	0
T166	0	21	0	0
T167	0	9	0	0
T168	0	3	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1523	0	0
T11	464020	0	0	0
T64	1421	0	0	0
T69	210708	54	0	0
T97	0	6	0	0
T98	0	40	0	0
T131	0	47	0	0
T132	0	28	0	0
T134	0	9	0	0
T144	536427	0	0	0
T145	211447	0	0	0
T146	8503	0	0	0
T147	206303	0	0	0
T148	274104	0	0	0
T149	377246	0	0	0
T150	29340	0	0	0
T151	0	18	0	0
T166	0	47	0	0
T167	0	31	0	0
T168	0	6	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1337	0	0
T11	464020	0	0	0
T64	1421	0	0	0
T69	210708	27	0	0
T97	0	13	0	0
T98	0	33	0	0
T131	0	30	0	0
T132	0	29	0	0
T134	0	2	0	0
T144	536427	0	0	0
T145	211447	0	0	0
T146	8503	0	0	0
T147	206303	0	0	0
T148	274104	0	0	0
T149	377246	0	0	0
T150	29340	0	0	0
T151	0	8	0	0
T166	0	40	0	0
T167	0	12	0	0
T168	0	4	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1453	0	0
T11	464020	0	0	0
T64	1421	0	0	0
T69	210708	56	0	0
T97	0	17	0	0
T98	0	49	0	0
T131	0	41	0	0
T132	0	47	0	0
T144	536427	0	0	0
T145	211447	0	0	0
T146	8503	0	0	0
T147	206303	0	0	0
T148	274104	0	0	0
T149	377246	0	0	0
T150	29340	0	0	0
T151	0	3	0	0
T166	0	30	0	0
T167	0	56	0	0
T168	0	4	0	0
T169	0	55	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1529	0	0
T11	464020	0	0	0
T64	1421	0	0	0
T69	210708	84	0	0
T97	0	27	0	0
T98	0	20	0	0
T131	0	36	0	0
T132	0	44	0	0
T134	0	2	0	0
T144	536427	0	0	0
T145	211447	0	0	0
T146	8503	0	0	0
T147	206303	0	0	0
T148	274104	0	0	0
T149	377246	0	0	0
T150	29340	0	0	0
T151	0	7	0	0
T166	0	18	0	0
T167	0	18	0	0
T168	0	8	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1383	0	0
T11	464020	0	0	0
T64	1421	0	0	0
T69	210708	60	0	0
T97	0	22	0	0
T98	0	31	0	0
T131	0	60	0	0
T132	0	36	0	0
T134	0	5	0	0
T144	536427	0	0	0
T145	211447	0	0	0
T146	8503	0	0	0
T147	206303	0	0	0
T148	274104	0	0	0
T149	377246	0	0	0
T150	29340	0	0	0
T151	0	10	0	0
T166	0	7	0	0
T169	0	11	0	0
T170	0	39	0	0