Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172932 |
1 |
|
|
T1 |
1523 |
|
T7 |
406 |
|
T19 |
249 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
85613 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
67012 |
1 |
|
|
T1 |
507 |
|
T7 |
400 |
|
T19 |
246 |
seven_bytes |
2909 |
1 |
|
|
T1 |
27 |
|
T57 |
19 |
|
T17 |
4 |
six_bytes |
2875 |
1 |
|
|
T1 |
37 |
|
T57 |
15 |
|
T17 |
5 |
five_bytes |
2944 |
1 |
|
|
T1 |
31 |
|
T57 |
26 |
|
T17 |
1 |
four_bytes |
2980 |
1 |
|
|
T1 |
28 |
|
T57 |
22 |
|
T17 |
8 |
three_bytes |
2885 |
1 |
|
|
T1 |
28 |
|
T57 |
12 |
|
T17 |
3 |
two_bytes |
2798 |
1 |
|
|
T1 |
28 |
|
T57 |
12 |
|
T17 |
8 |
one_byte |
2916 |
1 |
|
|
T1 |
34 |
|
T57 |
15 |
|
T17 |
2 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
169524 |
1 |
|
|
T1 |
1499 |
|
T7 |
394 |
|
T19 |
243 |
auto[1] |
3408 |
1 |
|
|
T1 |
24 |
|
T7 |
12 |
|
T19 |
6 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172932 |
1 |
|
|
T1 |
1523 |
|
T7 |
406 |
|
T19 |
249 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172924 |
1 |
|
|
T1 |
1523 |
|
T7 |
406 |
|
T19 |
249 |
auto[1] |
8 |
1 |
|
|
T169 |
1 |
|
T170 |
1 |
|
T171 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1211 |
1 |
|
|
T1 |
6 |
|
T7 |
6 |
|
T19 |
3 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3408 |
1 |
|
|
T1 |
24 |
|
T7 |
12 |
|
T19 |
6 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
183244 |
1 |
|
|
T1 |
2078 |
|
T7 |
807 |
|
T16 |
536 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
93557 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
67608 |
1 |
|
|
T1 |
161 |
|
T7 |
370 |
|
T16 |
526 |
seven_bytes |
3231 |
1 |
|
|
T1 |
47 |
|
T7 |
10 |
|
T57 |
29 |
six_bytes |
3122 |
1 |
|
|
T1 |
42 |
|
T7 |
11 |
|
T57 |
32 |
five_bytes |
3180 |
1 |
|
|
T1 |
64 |
|
T7 |
11 |
|
T57 |
38 |
four_bytes |
3154 |
1 |
|
|
T1 |
58 |
|
T7 |
12 |
|
T57 |
43 |
three_bytes |
3161 |
1 |
|
|
T1 |
60 |
|
T7 |
8 |
|
T57 |
40 |
two_bytes |
3118 |
1 |
|
|
T1 |
46 |
|
T7 |
9 |
|
T57 |
42 |
one_byte |
3113 |
1 |
|
|
T1 |
48 |
|
T7 |
15 |
|
T57 |
57 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
179702 |
1 |
|
|
T1 |
2052 |
|
T7 |
793 |
|
T16 |
516 |
auto[1] |
3542 |
1 |
|
|
T1 |
26 |
|
T7 |
14 |
|
T16 |
20 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
183244 |
1 |
|
|
T1 |
2078 |
|
T7 |
807 |
|
T16 |
536 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
183232 |
1 |
|
|
T1 |
2078 |
|
T7 |
807 |
|
T16 |
536 |
auto[1] |
12 |
1 |
|
|
T172 |
2 |
|
T173 |
1 |
|
T171 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1232 |
1 |
|
|
T1 |
5 |
|
T7 |
5 |
|
T16 |
10 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3542 |
1 |
|
|
T1 |
26 |
|
T7 |
14 |
|
T16 |
20 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
354622 |
1 |
|
|
T1 |
3732 |
|
T2 |
121 |
|
T7 |
1175 |
auto[1] |
504 |
1 |
|
|
T8 |
66 |
|
T9 |
47 |
|
T10 |
69 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
181435 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
130185 |
1 |
|
|
T1 |
425 |
|
T2 |
120 |
|
T7 |
460 |
seven_bytes |
6196 |
1 |
|
|
T1 |
91 |
|
T7 |
22 |
|
T57 |
87 |
six_bytes |
6254 |
1 |
|
|
T1 |
80 |
|
T7 |
21 |
|
T57 |
82 |
five_bytes |
6172 |
1 |
|
|
T1 |
97 |
|
T7 |
25 |
|
T57 |
64 |
four_bytes |
6366 |
1 |
|
|
T1 |
98 |
|
T7 |
25 |
|
T57 |
63 |
three_bytes |
6173 |
1 |
|
|
T1 |
97 |
|
T7 |
24 |
|
T57 |
72 |
two_bytes |
6138 |
1 |
|
|
T1 |
110 |
|
T7 |
21 |
|
T57 |
62 |
one_byte |
6207 |
1 |
|
|
T1 |
69 |
|
T7 |
23 |
|
T57 |
73 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
348381 |
1 |
|
|
T1 |
3672 |
|
T2 |
119 |
|
T7 |
1151 |
auto[1] |
6745 |
1 |
|
|
T1 |
60 |
|
T2 |
2 |
|
T7 |
24 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
355126 |
1 |
|
|
T1 |
3732 |
|
T2 |
121 |
|
T7 |
1175 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
355102 |
1 |
|
|
T1 |
3732 |
|
T2 |
121 |
|
T7 |
1175 |
auto[1] |
24 |
1 |
|
|
T16 |
1 |
|
T57 |
1 |
|
T8 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2358 |
1 |
|
|
T1 |
17 |
|
T2 |
1 |
|
T7 |
8 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6745 |
1 |
|
|
T1 |
60 |
|
T2 |
2 |
|
T7 |
24 |