Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

149124426

1

T1

71991

T2

11110

T3

22

full_word

111637286

1

T1

225419

T2

12361

T3

9

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	260761422	1			T1	297410		T2	23471		T3	31
auto[TlIntgErrCmd]	99	1			T116	1		T117	1		T118	7
auto[TlIntgErrData]	97	1			T116	3		T117	3		T118	9
auto[TlIntgErrBoth]	94	1			T116	6		T117	6		T118	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

136167551

1

T1

131621

T2

16697

T3

1

auto[1]

124594161

1

T1

165789

T2

6774

T3

30

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	92514638	1			T1	55329		T2	8181		T15	2174
auto[TlIntgErrNone]	partial	auto[1]	56609514	1			T1	16662		T2	2929		T3	22
auto[TlIntgErrNone]	full_word	auto[0]	43652768	1			T1	76292		T2	8516		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	67984502	1			T1	149127		T2	3845		T3	8
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T116	1		T118	3		T180	4
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T117	1		T118	3		T180	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T118	1		T181	1		T174	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T179	2		T182	1		-	-
auto[TlIntgErrData]	partial	auto[0]	47	1			T116	1		T118	2		T180	4
auto[TlIntgErrData]	partial	auto[1]	45	1			T116	2		T117	3		T118	5
auto[TlIntgErrData]	full_word	auto[0]	3	1			T118	2		T183	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1			T184	1		T182	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T116	1		T117	4		T118	3
auto[TlIntgErrBoth]	partial	auto[1]	44	1			T116	5		T117	2		T118	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T178	1		T184	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T179	1		-	-		-	-