Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

164008205

1

T1

10

T2

409

T3

16229

full_word

120881526

1

T1

5

T2

660

T3

21744

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	284889371	1			T1	15		T2	1069		T3	37973
auto[TlIntgErrCmd]	132	1			T128	10		T129	8		T130	2
auto[TlIntgErrData]	118	1			T128	6		T129	6		T130	4
auto[TlIntgErrBoth]	110	1			T128	4		T129	6		T130	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

148037189

1

T1

1

T2

755

T3

25044

auto[1]

136852542

1

T1

14

T2

314

T3

12929

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	100470589	1			T2	252		T3	10102		T17	322048
auto[TlIntgErrNone]	partial	auto[1]	63537290	1			T1	10		T2	157		T3	6127
auto[TlIntgErrNone]	full_word	auto[0]	47566428	1			T1	1		T2	503		T3	14942
auto[TlIntgErrNone]	full_word	auto[1]	73315064	1			T1	4		T2	157		T3	6802
auto[TlIntgErrCmd]	partial	auto[0]	53	1			T128	3		T129	3		T130	1
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T128	7		T129	4		T179	4
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T130	1		T182	1		T183	2
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T129	1		T182	1		T184	2
auto[TlIntgErrData]	partial	auto[0]	65	1			T128	3		T129	3		T130	2
auto[TlIntgErrData]	partial	auto[1]	43	1			T128	2		T129	3		T130	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T184	1		T181	1		T185	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T128	1		T130	1		T179	2
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T128	1		T129	4		T130	3
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T128	2		T129	2		T130	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T128	1		T182	1		T183	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T182	1		T181	1		T186	1