Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.05	87.50	92.68			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_app_intf.u_appid_arb	95.05	87.50	92.68			100.00	100.00

---

Module Instance : tb.dut.u_app_intf.u_appid_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.05	87.50	92.68			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.05	87.50	92.68			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.27	94.57	86.30		44.44	91.01	100.00	u_app_intf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		32	28	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	0	0.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	3	3
87	0	3
89	3	3
97	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	0	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	41	38	92.68
Logical	41	38	92.68
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T12
0	1	Covered	T2,T7,T8
1	0	Covered	T7,T12,T8

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T8
0	1	Covered	T7,T12,T8
1	0	Covered	T7,T8,T14

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T12
0	1	Unreachable
1	0	Covered	T2,T7,T12

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T12,T8
1	Covered	T2,T7,T12

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T12,T8
1	Covered	T7,T12,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T2,T7,T12
1	Covered	T2,T7,T12

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T12,T8
1	Covered	T2,T7,T12

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T12,T8
1	Covered	T7,T12,T8

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T2,T7,T12
1	Covered	T2,T7,T12

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T12,T8
1	0	Covered	T2,T7,T8
1	1	Covered	T7,T8,T14

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T12,T8
1	0	Covered	T7,T8,T14
1	1	Covered	T7,T8,T14

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T12
1	0	Not Covered
1	1	Covered	T2,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T12
1	0	Covered	T7,T8,T14
1	1	Covered	T2,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T12,T8
1	0	Covered	T7,T8,T14
1	1	Covered	T7,T8,T14

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T12
1	0	Covered	T2,T7,T8
1	1	Not Covered

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T7,T12
1	1	Covered	T2,T7,T8

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T12
0	Covered	T7,T12,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T12
0	Covered	T7,T12,T8

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T12,T8
0	Covered	T7,T12,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T12,T8
0	Covered	T7,T12,T8

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T12
0	Covered	T2,T7,T12

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T12
0	Covered	T2,T7,T12

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1474723140	1474522125	0	0
CheckNGreaterZero_A	933	933	0	0
GntImpliesReady_A	1474723140	7289	0	0
GntImpliesValid_A	1474723140	7289	0	0
GrantKnown_A	1474723140	1474522125	0	0
IdxKnown_A	1474723140	1474522125	0	0
IndexIsCorrect_A	1474723140	7289	0	0
NoReadyValidNoGrant_A	1474723140	1470391356	0	0
Priority_A	1474723140	4130769	0	0
ReadyAndValidImplyGrant_A	1474723140	7289	0	0
ReqAndReadyImplyGrant_A	1474723140	7289	0	0
ReqImpliesValid_A	1474723140	4130769	0	0
ValidKnown_A	1474723140	1474522125	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	1474522125	0	0
T1	1477	1396	0	0
T2	15751	15669	0	0
T3	362878	362803	0	0
T7	60114	59947	0	0
T8	321414	321340	0	0
T12	4078	3961	0	0
T13	2702	2560	0	0
T14	281236	281141	0	0
T17	195600	195594	0	0
T33	193415	193407	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	933	933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T33	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	7289	0	0
T2	15751	1	0	0
T3	362878	0	0	0
T7	60114	5	0	0
T8	321414	27	0	0
T12	4078	0	0	0
T13	2702	1	0	0
T14	281236	79	0	0
T17	195600	0	0	0
T18	0	22	0	0
T21	0	67	0	0
T27	0	4	0	0
T33	193415	0	0	0
T34	202556	0	0	0
T36	0	8	0	0
T37	0	35	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	7289	0	0
T2	15751	1	0	0
T3	362878	0	0	0
T7	60114	5	0	0
T8	321414	27	0	0
T12	4078	0	0	0
T13	2702	1	0	0
T14	281236	79	0	0
T17	195600	0	0	0
T18	0	22	0	0
T21	0	67	0	0
T27	0	4	0	0
T33	193415	0	0	0
T34	202556	0	0	0
T36	0	8	0	0
T37	0	35	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	1474522125	0	0
T1	1477	1396	0	0
T2	15751	15669	0	0
T3	362878	362803	0	0
T7	60114	59947	0	0
T8	321414	321340	0	0
T12	4078	3961	0	0
T13	2702	2560	0	0
T14	281236	281141	0	0
T17	195600	195594	0	0
T33	193415	193407	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	1474522125	0	0
T1	1477	1396	0	0
T2	15751	15669	0	0
T3	362878	362803	0	0
T7	60114	59947	0	0
T8	321414	321340	0	0
T12	4078	3961	0	0
T13	2702	2560	0	0
T14	281236	281141	0	0
T17	195600	195594	0	0
T33	193415	193407	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	7289	0	0
T2	15751	1	0	0
T3	362878	0	0	0
T7	60114	5	0	0
T8	321414	27	0	0
T12	4078	0	0	0
T13	2702	1	0	0
T14	281236	79	0	0
T17	195600	0	0	0
T18	0	22	0	0
T21	0	67	0	0
T27	0	4	0	0
T33	193415	0	0	0
T34	202556	0	0	0
T36	0	8	0	0
T37	0	35	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	1470391356	0	0
T1	1477	1396	0	0
T2	15751	13570	0	0
T3	362878	362803	0	0
T7	60114	57688	0	0
T8	321414	316387	0	0
T12	4078	2318	0	0
T13	2702	460	0	0
T14	281236	280341	0	0
T17	195600	195594	0	0
T33	193415	193407	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	4130769	0	0
T2	15751	2099	0	0
T3	362878	0	0	0
T7	60114	2259	0	0
T8	321414	4953	0	0
T12	4078	1643	0	0
T13	2702	2100	0	0
T14	281236	8000	0	0
T17	195600	0	0	0
T21	0	10314	0	0
T30	0	806	0	0
T31	0	1908	0	0
T33	193415	0	0	0
T34	202556	0	0	0
T36	0	984	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	7289	0	0
T2	15751	1	0	0
T3	362878	0	0	0
T7	60114	5	0	0
T8	321414	27	0	0
T12	4078	0	0	0
T13	2702	1	0	0
T14	281236	79	0	0
T17	195600	0	0	0
T18	0	22	0	0
T21	0	67	0	0
T27	0	4	0	0
T33	193415	0	0	0
T34	202556	0	0	0
T36	0	8	0	0
T37	0	35	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	7289	0	0
T2	15751	1	0	0
T3	362878	0	0	0
T7	60114	5	0	0
T8	321414	27	0	0
T12	4078	0	0	0
T13	2702	1	0	0
T14	281236	79	0	0
T17	195600	0	0	0
T18	0	22	0	0
T21	0	67	0	0
T27	0	4	0	0
T33	193415	0	0	0
T34	202556	0	0	0
T36	0	8	0	0
T37	0	35	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	4130769	0	0
T2	15751	2099	0	0
T3	362878	0	0	0
T7	60114	2259	0	0
T8	321414	4953	0	0
T12	4078	1643	0	0
T13	2702	2100	0	0
T14	281236	8000	0	0
T17	195600	0	0	0
T21	0	10314	0	0
T30	0	806	0	0
T31	0	1908	0	0
T33	193415	0	0	0
T34	202556	0	0	0
T36	0	984	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	1474522125	0	0
T1	1477	1396	0	0
T2	15751	15669	0	0
T3	362878	362803	0	0
T7	60114	59947	0	0
T8	321414	321340	0	0
T12	4078	3961	0	0
T13	2702	2560	0	0
T14	281236	281141	0	0
T17	195600	195594	0	0
T33	193415	193407	0	0