Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	1474723140	203725	0	0
RunThenComplete_M	1474723140	2089230	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	203725	0	0
T2	15751	2	0	0
T3	362878	36	0	0
T7	60114	15	0	0
T8	321414	107	0	0
T12	4078	0	0	0
T13	2702	0	0	0
T14	281236	513	0	0
T17	195600	374	0	0
T21	0	176	0	0
T33	193415	374	0	0
T34	202556	390	0	0
T35	0	2265	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474723140	2089230	0	0
T2	15751	8	0	0
T3	362878	186	0	0
T7	60114	86	0	0
T8	321414	545	0	0
T12	4078	0	0	0
T13	2702	1	0	0
T14	281236	6119	0	0
T17	195600	5526	0	0
T21	0	883	0	0
T33	193415	5526	0	0
T34	202556	5542	0	0