Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1476098031	198862717	0	0
DepthKnown_A	1476098031	1475842092	0	0
RvalidKnown_A	1476098031	1475842092	0	0
WreadyKnown_A	1476098031	1475842092	0	0
gen_passthru_fifo.paramCheckPass	1148	1148	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476098031	198862717	0	0
T1	1477	15	0	0
T2	15751	505	0	0
T3	362878	20394	0	0
T7	60114	8638	0	0
T8	321414	54903	0	0
T12	4078	98	0	0
T13	2702	89	0	0
T14	281236	711526	0	0
T17	195600	648551	0	0
T33	193415	632960	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476098031	1475842092	0	0
T1	1477	1396	0	0
T2	15751	15669	0	0
T3	362878	362803	0	0
T7	60114	59947	0	0
T8	321414	321340	0	0
T12	4078	3961	0	0
T13	2702	2560	0	0
T14	281236	281141	0	0
T17	195600	195594	0	0
T33	193415	193407	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476098031	1475842092	0	0
T1	1477	1396	0	0
T2	15751	15669	0	0
T3	362878	362803	0	0
T7	60114	59947	0	0
T8	321414	321340	0	0
T12	4078	3961	0	0
T13	2702	2560	0	0
T14	281236	281141	0	0
T17	195600	195594	0	0
T33	193415	193407	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476098031	1475842092	0	0
T1	1477	1396	0	0
T2	15751	15669	0	0
T3	362878	362803	0	0
T7	60114	59947	0	0
T8	321414	321340	0	0
T12	4078	3961	0	0
T13	2702	2560	0	0
T14	281236	281141	0	0
T17	195600	195594	0	0
T33	193415	193407	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T33	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1476098031	288263604	0	0
DepthKnown_A	1476098031	1475842092	0	0
RvalidKnown_A	1476098031	1475842092	0	0
WreadyKnown_A	1476098031	1475842092	0	0
gen_passthru_fifo.paramCheckPass	1148	1148	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476098031	288263604	0	0
T1	1477	66	0	0
T2	15751	505	0	0
T3	362878	62586	0	0
T7	60114	8638	0	0
T8	321414	54903	0	0
T12	4078	418	0	0
T13	2702	89	0	0
T14	281236	711526	0	0
T17	195600	648551	0	0
T33	193415	632960	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476098031	1475842092	0	0
T1	1477	1396	0	0
T2	15751	15669	0	0
T3	362878	362803	0	0
T7	60114	59947	0	0
T8	321414	321340	0	0
T12	4078	3961	0	0
T13	2702	2560	0	0
T14	281236	281141	0	0
T17	195600	195594	0	0
T33	193415	193407	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476098031	1475842092	0	0
T1	1477	1396	0	0
T2	15751	15669	0	0
T3	362878	362803	0	0
T7	60114	59947	0	0
T8	321414	321340	0	0
T12	4078	3961	0	0
T13	2702	2560	0	0
T14	281236	281141	0	0
T17	195600	195594	0	0
T33	193415	193407	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476098031	1475842092	0	0
T1	1477	1396	0	0
T2	15751	15669	0	0
T3	362878	362803	0	0
T7	60114	59947	0	0
T8	321414	321340	0	0
T12	4078	3961	0	0
T13	2702	2560	0	0
T14	281236	281141	0	0
T17	195600	195594	0	0
T33	193415	193407	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T33	1	1	0	0