Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1476098031	199450	0	0
entropy_period_rd_A	1476098031	1803	0	0
intr_enable_rd_A	1476098031	2455	0	0
prefix_0_rd_A	1476098031	1367	0	0
prefix_10_rd_A	1476098031	1480	0	0
prefix_1_rd_A	1476098031	1500	0	0
prefix_2_rd_A	1476098031	1438	0	0
prefix_3_rd_A	1476098031	1277	0	0
prefix_4_rd_A	1476098031	1341	0	0
prefix_5_rd_A	1476098031	1335	0	0
prefix_6_rd_A	1476098031	1290	0	0
prefix_7_rd_A	1476098031	1512	0	0
prefix_8_rd_A	1476098031	1330	0	0
prefix_9_rd_A	1476098031	1250	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476098031	199450	0	0
T25	0	8462	0	0
T69	390501	31942	0	0
T70	0	45468	0	0
T128	0	2	0	0
T135	0	110701	0	0
T136	0	1	0	0
T137	0	4	0	0
T138	0	6	0	0
T139	0	1	0	0
T140	0	17	0	0
T142	53325	0	0	0
T143	67580	0	0	0
T144	472481	0	0	0
T145	116848	0	0	0
T146	146572	0	0	0
T147	134946	0	0	0
T148	56306	0	0	0
T149	478550	0	0	0
T150	67559	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476098031	1803	0	0
T86	5289	13	0	0
T87	5982	33	0	0
T88	5079	6	0	0
T89	9013	52	0	0
T127	13259	70	0	0
T136	4580	17	0	0
T138	8014	11	0	0
T139	3864	14	0	0
T163	10727	20	0	0
T164	2460	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476098031	2455	0	0
T86	5289	30	0	0
T87	5982	21	0	0
T88	5079	4	0	0
T131	1443	19	0	0
T132	1419	21	0	0
T136	4580	8	0	0
T138	8014	32	0	0
T139	3864	1	0	0
T163	10727	19	0	0
T165	1681	12	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476098031	1367	0	0
T86	5289	7	0	0
T87	5982	19	0	0
T89	9013	34	0	0
T92	5813	26	0	0
T127	13259	60	0	0
T136	4580	3	0	0
T138	8014	9	0	0
T139	3864	11	0	0
T163	10727	25	0	0
T164	2460	6	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476098031	1480	0	0
T86	5289	12	0	0
T87	5982	20	0	0
T88	5079	3	0	0
T89	9013	32	0	0
T127	13259	68	0	0
T136	4580	14	0	0
T138	8014	21	0	0
T139	3864	10	0	0
T163	10727	18	0	0
T164	2460	5	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476098031	1500	0	0
T86	5289	10	0	0
T87	5982	6	0	0
T88	5079	13	0	0
T89	9013	30	0	0
T136	4580	1	0	0
T138	8014	20	0	0
T139	3864	7	0	0
T163	10727	45	0	0
T164	2460	1	0	0
T166	14546	5	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476098031	1438	0	0
T86	5289	1	0	0
T87	5982	8	0	0
T88	5079	27	0	0
T89	9013	27	0	0
T127	13259	76	0	0
T136	4580	2	0	0
T138	8014	9	0	0
T139	3864	11	0	0
T163	10727	6	0	0
T164	2460	7	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476098031	1277	0	0
T86	5289	18	0	0
T87	5982	19	0	0
T88	5079	3	0	0
T89	9013	29	0	0
T136	4580	2	0	0
T138	8014	17	0	0
T139	3864	8	0	0
T163	10727	46	0	0
T164	2460	1	0	0
T166	14546	16	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476098031	1341	0	0
T86	5289	17	0	0
T87	5982	17	0	0
T88	5079	5	0	0
T89	9013	32	0	0
T127	13259	58	0	0
T136	4580	10	0	0
T138	8014	17	0	0
T139	3864	7	0	0
T163	10727	16	0	0
T164	2460	10	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476098031	1335	0	0
T86	5289	9	0	0
T87	5982	10	0	0
T88	5079	11	0	0
T89	9013	39	0	0
T127	13259	59	0	0
T136	4580	10	0	0
T138	8014	21	0	0
T139	3864	7	0	0
T163	10727	43	0	0
T164	2460	4	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476098031	1290	0	0
T86	5289	21	0	0
T87	5982	24	0	0
T88	5079	11	0	0
T89	9013	20	0	0
T92	5813	23	0	0
T127	13259	45	0	0
T136	4580	5	0	0
T138	8014	16	0	0
T139	3864	6	0	0
T163	10727	18	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476098031	1512	0	0
T86	5289	16	0	0
T87	5982	9	0	0
T88	5079	17	0	0
T89	9013	32	0	0
T127	13259	46	0	0
T136	4580	10	0	0
T138	8014	21	0	0
T139	3864	17	0	0
T163	10727	53	0	0
T164	2460	8	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476098031	1330	0	0
T86	5289	15	0	0
T87	5982	9	0	0
T88	5079	9	0	0
T89	9013	23	0	0
T92	5813	17	0	0
T127	13259	60	0	0
T136	4580	8	0	0
T138	8014	14	0	0
T139	3864	9	0	0
T163	10727	29	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1476098031	1250	0	0
T86	5289	23	0	0
T87	5982	3	0	0
T88	5079	14	0	0
T89	9013	17	0	0
T127	13259	41	0	0
T136	4580	15	0	0
T138	8014	25	0	0
T139	3864	8	0	0
T163	10727	13	0	0
T164	2460	3	0	0