Unified Coverage Report :: Module :: sha3pad

Module : sha3pad

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.93	99.41	88.37		76.19	95.70	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_pad	94.47	99.41	88.37		88.89	95.70	100.00

---

Module Instance : tb.dut.u_sha3.u_pad

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.47	99.41	88.37		88.89	95.70	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.42	99.45	88.37	100.00	88.89	95.79	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	97.56	88.89		100.00	93.33	100.00	u_sha3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prefix_slicer	100.00	100.00					100.00
u_sentmsg_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : sha3pad

	Line No.	Total	Covered	Percent
TOTAL		170	169	99.41
ALWAYS	157	6	6	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
ALWAYS	267	6	6	100.00
ALWAYS	279	3	3	100.00
CONT_ASSIGN	286	1	1	100.00
ALWAYS	293	3	3	100.00
ALWAYS	298	76	75	98.68
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
ALWAYS	558	4	4	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	588	1	1	100.00
ALWAYS	591	5	5	100.00
ALWAYS	603	5	5	100.00
ALWAYS	615	5	5	100.00
ALWAYS	664	10	10	100.00
ALWAYS	680	17	17	100.00
ALWAYS	779	6	6	100.00
ALWAYS	788	6	6	100.00
ALWAYS	798	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
209	1	1
213	1	1
236	1	1
242	1	1
247	1	1
257	1	1
267	1	1
268	1	1
269	1	1
270	1	1
271	1	1
272	1	1
			MISSING_ELSE
279	3	3
286	1	1
293	2	2
294	1	1
298	1	1
301	1	1
302	1	1
304	1	1
306	1	1
307	1	1
309	1	1
310	1	1
312	1	1
314	1	1
316	1	1
325	1	1
327	1	1
328	1	1
330	1	1
333	1	1
345	1	1
347	1	1
348	1	1
350	1	1
351	1	1
352	1	1
354	1	1
356	1	1
361	1	1
363	1	1
364	1	1
366	1	1
375	1	1
377	1	1
378	1	1
380	1	1
381	1	1
383	1	1
385	1	1
386	1	1
387	1	1
388	1	1
389	1	1
392	1	1
394	1	1
400	1	1
402	1	1
403	1	1
405	1	1
414	1	1
416	1	1
418	1	1
421	1	1
424	1	1
425	1	1
426	1	1
427	1	1
428	1	1
430	0	1
435	1	1
437	1	1
438	1	1
447	1	1
451	1	1
452	1	1
454	1	1
455	1	1
456	1	1
458	1	1
460	1	1
466	1	1
467	1	1
469	1	1
470	1	1
472	1	1
474	1	1
480	1	1
481	1	1
494	1	1
495	1	1
			MISSING_ELSE
509	1	1
520	1	1
538	1	1
558	1	1
559	1	1
560	1	1
561	1	1
578	1	1
588	1	1
591	1	1
592	1	1
593	1	1
594	1	1
595	1	1
603	1	1
604	1	1
605	1	1
606	1	1
607	1	1
615	1	1
616	1	1
617	1	1
618	1	1
619	1	1
664	1	1
665	1	1
666	1	1
667	1	1
668	1	1
669	1	1
671	1	1
672	1	1
673	1	1
674	1	1
			MISSING_ELSE
680	1	1
682	1	1
683	1	1
686	1	1
687	1	1
690	1	1
691	1	1
694	1	1
695	1	1
698	1	1
699	1	1
702	1	1
703	1	1
706	1	1
707	1	1
710	1	1
711	1	1
779	1	1
780	1	1
781	1	1
782	1	1
783	1	1
784	1	1
			MISSING_ELSE
788	1	1
789	1	1
790	1	1
791	1	1
792	1	1
793	1	1
			MISSING_ELSE
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE

---

Cond Coverage for Module : sha3pad

	Total	Covered	Percent
Conditions	43	38	88.37
Logical	43	38	88.37
Non-Logical	0	0
Event	0	0

 LINE       209
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION ((mode_i == CShake) ? 1'b1 : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       236
 SUB-EXPRESSION (mode_i == CShake)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       242
 EXPRESSION ((sent_message == block_addr_limit) ? 1'b1 : 1'b0)
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       242
 SUB-EXPRESSION (sent_message == block_addr_limit)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       247
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       257
 EXPRESSION ((&msg_strb_i) != 1'b1)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION (((sent_message + 1'b1) == block_addr_limit) ? 1'b1 : 1'b0)
             ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 SUB-EXPRESSION ((sent_message + 1'b1) == block_addr_limit)
                ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       377
 EXPRESSION (msg_valid_i && msg_partial)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       388
 EXPRESSION (process_latched || process_i)
             -------1-------    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6

 LINE       418
 EXPRESSION (keccak_ack && end_of_block)
             -----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       588
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       604
 EXPRESSION (msg_valid_i & ((~hold_msg)) & ((~en_msgbuf)))
             -----1-----   ------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T62,T43
1	1	0	Covered	T1,T3,T6
1	1	1	Covered	T1,T2,T3

 LINE       616
 EXPRESSION (en_msgbuf | (keccak_ready_i & ((~hold_msg))))
             ----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       616
 SUB-EXPRESSION (keccak_ready_i & ((~hold_msg)))
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : sha3pad

Summary for FSM :: st

	Total	Covered	Percent
States	10	10	100.00	(Not included in score)
Transitions	21	16	76.19
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StMessage	330	Covered	T1,T2,T3
StMessageWait	383	Covered	T1,T2,T3
StPad	389	Covered	T1,T2,T3
StPad01	427	Covered	T1,T2,T3
StPadFlush	435	Covered	T1,T2,T3
StPadIdle	333	Covered	T1,T2,T3
StPadRun	421	Covered	T1,T3,T6
StPrefix	328	Covered	T1,T2,T6
StPrefixWait	348	Covered	T1,T2,T6
StTerminalError	495	Covered	T12,T13,T14

transitions	Line No.	Covered	Tests
StMessage->StMessageWait	383	Covered	T1,T2,T3
StMessage->StPad	389	Covered	T1,T2,T3
StMessage->StTerminalError	495	Covered	T12,T14,T32
StMessageWait->StMessage	403	Covered	T1,T2,T3
StMessageWait->StTerminalError	495	Covered	T27,T55,T63
StPad->StPad01	427	Covered	T1,T2,T3
StPad->StPadRun	421	Covered	T1,T3,T6
StPad->StTerminalError	495	Not Covered
StPad01->StPadFlush	452	Covered	T1,T2,T3
StPad01->StTerminalError	495	Not Covered
StPadFlush->StPadIdle	470	Covered	T1,T2,T3
StPadFlush->StTerminalError	495	Not Covered
StPadIdle->StMessage	330	Covered	T1,T3,T6
StPadIdle->StPrefix	328	Covered	T1,T2,T6
StPadIdle->StTerminalError	495	Covered	T13,T46,T47
StPadRun->StPadFlush	435	Covered	T1,T3,T6
StPadRun->StTerminalError	495	Not Covered
StPrefix->StPrefixWait	348	Covered	T1,T2,T6
StPrefix->StTerminalError	495	Not Covered
StPrefixWait->StMessage	364	Covered	T1,T2,T6
StPrefixWait->StTerminalError	495	Covered	T54,T59,T56

---

Branch Coverage for Module : sha3pad

	Line No.	Total	Covered	Percent
Branches		93	89	95.70
TERNARY	213	2	2	100.00
TERNARY	236	2	2	100.00
TERNARY	242	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	588	2	2	100.00
CASE	157	6	5	83.33
IF	267	4	4	100.00
IF	279	2	2	100.00
IF	293	2	2	100.00
CASE	316	23	22	95.65
IF	494	2	2	100.00
CASE	558	4	3	75.00
CASE	591	5	5	100.00
CASE	603	5	5	100.00
CASE	615	5	5	100.00
IF	664	4	4	100.00
IF	779	4	4	100.00
IF	788	4	4	100.00
IF	798	4	4	100.00
CASE	680	9	8	88.89

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	213	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	236	((mode_i == CShake)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	242	((sent_message == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(((sent_message + 1'b1) == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	588	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	157	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T1,T2,T3
L224	Covered	T1,T6,T38
L256	Covered	T1,T2,T3
L384	Covered	T2,T6,T36
L512	Covered	T1,T3,T38
default	Not Covered

	LineNo.	Expression
-1-:	267	if ((!rst_ni))
-2-:	269	if (process_i)
-3-:	271	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	279	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	293	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	316	case (st)
-2-:	325	if (start_i)
-3-:	327	if (mode_eq_cshake)
-4-:	347	if (sent_blocksize)
-5-:	363	if (keccak_complete_i)
-6-:	377	if ((msg_valid_i && msg_partial))
-7-:	381	if (sent_blocksize)
-8-:	388	if ((process_latched || process_i))
-9-:	402	if (keccak_complete_i)
-10-:	418	if ((keccak_ack && end_of_block))
-11-:	426	if (keccak_ack)
-12-:	451	if (sent_blocksize)
-13-:	469	if (keccak_complete_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StPadIdle	1	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
StPadIdle	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T6
StPadIdle	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrefix	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
StPrefix	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
StPrefixWait	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
StPrefixWait	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
StMessage	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T3,T6
StMessage	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T1,T2,T3
StMessage	-	-	-	-	0	0	1	-	-	-	-	-	Covered	T1,T2,T3
StMessage	-	-	-	-	0	0	0	-	-	-	-	-	Covered	T1,T2,T3
StMessageWait	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T3
StMessageWait	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
StPad	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T3,T6
StPad	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T2,T3
StPad	-	-	-	-	-	-	-	-	0	0	-	-	Not Covered
StPadRun	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T6
StPad01	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
StPad01	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T3
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T30,T31,T33

	LineNo.	Expression
-1-:	494	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	558	case (mode_i)

Branches:

-1-	Status	Tests
Sha3	Covered	T1,T2,T3
Shake	Covered	T1,T2,T6
CShake	Covered	T1,T2,T6
default	Not Covered

	LineNo.	Expression
-1-:	591	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T1,T2,T3
MuxPrefix	Covered	T1,T2,T6
MuxFuncPad	Covered	T1,T2,T3
MuxZeroEnd	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	603	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T1,T2,T3
MuxPrefix	Covered	T1,T2,T6
MuxFuncPad	Covered	T1,T2,T3
MuxZeroEnd	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	615	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T1,T2,T3
MuxPrefix	Covered	T1,T2,T6
MuxFuncPad	Covered	T1,T2,T3
MuxZeroEnd	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	664	if ((!rst_ni))
-2-:	667	if (en_msgbuf)
-3-:	672	if (clr_msgbuf)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T6
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	779	if ((!rst_ni))
-2-:	781	if (start_i)
-3-:	783	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	788	if ((!rst_ni))
-2-:	790	if (start_i)
-3-:	792	if (process_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	798	if ((!rst_ni))
-2-:	800	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_o))
-3-:	802	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	680	case (msg_strb)

Branches:

-1-	Status	Tests
7'b0000000	Covered	T1,T2,T3
7'b0000001	Covered	T1,T3,T6
7'b0000011	Covered	T1,T3,T6
7'b0000111	Covered	T1,T3,T6
7'b0001111	Covered	T1,T3,T6
7'b0011111	Covered	T1,T3,T6
7'b0111111	Covered	T1,T3,T6
7'b1111111	Covered	T1,T3,T6
default	Not Covered

---

Assert Coverage for Module : sha3pad

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	4	4	100.00	4	100.00
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AbsorbedPulse_A	1417913732	194067	0	0
AlwaysPartialMsgBuf_M	1417913732	129191	0	0
CompleteBlockWhenProcess_A	1417913732	185637	0	0
DoneCondition_M	1417913732	194060	0	0
DonePulse_A	1417913732	194060	0	0
KeccakAddrInRange_A	1417913732	34458813	0	0
KeccakRunPulse_A	1417913732	2091077	0	0
MessageCondition_M	1417913732	31719870	0	0
ModeStableDuringOp_M	1417913732	33355	0	0
MsgReadyCondition_A	1417913732	946929753	0	0
MsgWidthidth_A	933	933	0	0
NoPartialMsgFifo_M	1417913732	31590679	0	0
Pad01NotAttheEndOfBlock_A	1417913732	186664	0	0
PartialEndOfMsg_M	1417913732	129191	0	0
PrefixLessThanBlock_A	933	933	0	0
ProcessCondition_M	1417913732	194071	0	0
ProcessPulse_A	1417913732	194071	0	0
StartCondition_M	1417913732	194113	0	0
StartProcessDoneMutex_a	1417913732	1417746344	0	0
StartPulse_A	1417913732	194113	0	0
StrengthStableDuringOp_M	1417913732	39514	0	0
u_state_regs_A	1417913732	1417746344	0	0

AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	194067	0	0
T1	573346	192	0	0
T2	74713	10	0	0
T3	335571	246	0	0
T6	503695	148	0	0
T7	37224	11	0	0
T8	122498	15	0	0
T34	528308	2265	0	0
T35	1239	0	0	0
T36	147780	310	0	0
T37	269630	96	0	0
T38	0	77	0	0

AlwaysPartialMsgBuf_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	129191	0	0
T1	573346	175	0	0
T2	74713	0	0	0
T3	335571	214	0	0
T6	503695	131	0	0
T7	37224	10	0	0
T8	122498	13	0	0
T20	0	21	0	0
T34	528308	890	0	0
T35	1239	0	0	0
T36	147780	270	0	0
T37	269630	79	0	0
T38	0	67	0	0

CompleteBlockWhenProcess_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	185637	0	0
T1	573346	181	0	0
T2	74713	10	0	0
T3	335571	219	0	0
T6	503695	139	0	0
T7	37224	10	0	0
T8	122498	14	0	0
T34	528308	2211	0	0
T35	1239	0	0	0
T36	147780	287	0	0
T37	269630	92	0	0
T38	0	72	0	0

DoneCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	194060	0	0
T1	573346	192	0	0
T2	74713	10	0	0
T3	335571	246	0	0
T6	503695	148	0	0
T7	37224	11	0	0
T8	122498	15	0	0
T34	528308	2265	0	0
T35	1239	0	0	0
T36	147780	310	0	0
T37	269630	96	0	0
T38	0	77	0	0

DonePulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	194060	0	0
T1	573346	192	0	0
T2	74713	10	0	0
T3	335571	246	0	0
T6	503695	148	0	0
T7	37224	11	0	0
T8	122498	15	0	0
T34	528308	2265	0	0
T35	1239	0	0	0
T36	147780	310	0	0
T37	269630	96	0	0
T38	0	77	0	0

KeccakAddrInRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	34458813	0	0
T1	573346	19395	0	0
T2	74713	510	0	0
T3	335571	48843	0	0
T6	503695	12304	0	0
T7	37224	950	0	0
T8	122498	1394	0	0
T34	528308	220643	0	0
T35	1239	0	0	0
T36	147780	71006	0	0
T37	269630	9578	0	0
T38	0	52519	0	0

KeccakRunPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	2091077	0	0
T1	573346	1041	0	0
T2	74713	30	0	0
T3	335571	5427	0	0
T6	503695	661	0	0
T7	37224	50	0	0
T8	122498	78	0	0
T34	528308	12979	0	0
T35	1239	0	0	0
T36	147780	5462	0	0
T37	269630	506	0	0
T38	0	2836	0	0

MessageCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	31719870	0	0
T1	573346	15085	0	0
T2	74713	170	0	0
T3	335571	47746	0	0
T6	503695	8673	0	0
T7	37224	759	0	0
T8	122498	1075	0	0
T34	528308	195716	0	0
T35	1239	0	0	0
T36	147780	69082	0	0
T37	269630	7286	0	0
T38	0	50644	0	0

ModeStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	33355	0	0
T1	573346	76	0	0
T2	74713	16	0	0
T3	335571	0	0	0
T6	503695	132	0	0
T7	37224	8	0	0
T8	122498	19	0	0
T20	0	33	0	0
T34	528308	1	0	0
T35	1239	0	0	0
T36	147780	0	0	0
T37	269630	43	0	0
T38	0	31	0	0
T42	0	8	0	0

MsgReadyCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	946929753	0	0
T1	573346	163659	0	0
T2	74713	64576	0	0
T3	335571	259242	0	0
T6	503695	272625	0	0
T7	37224	8920	0	0
T8	122498	75217	0	0
T34	528308	262162	0	0
T35	1239	0	0	0
T36	147780	739350	0	0
T37	269630	74318	0	0
T38	0	379219	0	0

MsgWidthidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	933	933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0

NoPartialMsgFifo_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	31590679	0	0
T1	573346	14910	0	0
T2	74713	170	0	0
T3	335571	47532	0	0
T6	503695	8542	0	0
T7	37224	749	0	0
T8	122498	1062	0	0
T34	528308	194826	0	0
T35	1239	0	0	0
T36	147780	68812	0	0
T37	269630	7207	0	0
T38	0	50577	0	0

Pad01NotAttheEndOfBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	186664	0	0
T1	573346	182	0	0
T2	74713	10	0	0
T3	335571	222	0	0
T6	503695	140	0	0
T7	37224	10	0	0
T8	122498	14	0	0
T34	528308	2217	0	0
T35	1239	0	0	0
T36	147780	289	0	0
T37	269630	93	0	0
T38	0	72	0	0

PartialEndOfMsg_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	129191	0	0
T1	573346	175	0	0
T2	74713	0	0	0
T3	335571	214	0	0
T6	503695	131	0	0
T7	37224	10	0	0
T8	122498	13	0	0
T20	0	21	0	0
T34	528308	890	0	0
T35	1239	0	0	0
T36	147780	270	0	0
T37	269630	79	0	0
T38	0	67	0	0

PrefixLessThanBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	933	933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0

ProcessCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	194071	0	0
T1	573346	192	0	0
T2	74713	10	0	0
T3	335571	246	0	0
T6	503695	148	0	0
T7	37224	11	0	0
T8	122498	15	0	0
T34	528308	2265	0	0
T35	1239	0	0	0
T36	147780	310	0	0
T37	269630	96	0	0
T38	0	77	0	0

ProcessPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	194071	0	0
T1	573346	192	0	0
T2	74713	10	0	0
T3	335571	246	0	0
T6	503695	148	0	0
T7	37224	11	0	0
T8	122498	15	0	0
T34	528308	2265	0	0
T35	1239	0	0	0
T36	147780	310	0	0
T37	269630	96	0	0
T38	0	77	0	0

StartCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	194113	0	0
T1	573346	192	0	0
T2	74713	10	0	0
T3	335571	246	0	0
T6	503695	148	0	0
T7	37224	11	0	0
T8	122498	15	0	0
T34	528308	2265	0	0
T35	1239	0	0	0
T36	147780	310	0	0
T37	269630	96	0	0
T38	0	77	0	0

StartProcessDoneMutex_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	1417746344	0	0
T1	573346	573294	0	0
T2	74713	74627	0	0
T3	335571	335566	0	0
T6	503695	503279	0	0
T7	37224	37147	0	0
T8	122498	122398	0	0
T34	528308	528298	0	0
T35	1239	1143	0	0
T36	147780	147772	0	0
T37	269630	269577	0	0

StartPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	194113	0	0
T1	573346	192	0	0
T2	74713	10	0	0
T3	335571	246	0	0
T6	503695	148	0	0
T7	37224	11	0	0
T8	122498	15	0	0
T34	528308	2265	0	0
T35	1239	0	0	0
T36	147780	310	0	0
T37	269630	96	0	0
T38	0	77	0	0

StrengthStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	39514	0	0
T1	573346	88	0	0
T2	74713	21	0	0
T3	335571	2	0	0
T6	503695	136	0	0
T7	37224	7	0	0
T8	122498	24	0	0
T34	528308	2	0	0
T35	1239	1	0	0
T36	147780	2	0	0
T37	269630	55	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	1417746344	0	0
T1	573346	573294	0	0
T2	74713	74627	0	0
T3	335571	335566	0	0
T6	503695	503279	0	0
T7	37224	37147	0	0
T8	122498	122398	0	0
T34	528308	528298	0	0
T35	1239	1143	0	0
T36	147780	147772	0	0
T37	269630	269577	0	0

---

Cover Directives for Properties: Details

Name	Attempts	Matches	Incomplete
StComplete_C	1417913732	18847821	0
StMessageFeed_C	1417913732	948984646	0
StPadSendMsg_C	1417913732	1993674	0
StPad_C	1417913732	186664	0

StComplete_C

Name	Attempts	Matches	Incomplete
Total	1417913732	18847821	0
T1	573346	18624	0
T2	74713	970	0
T3	335571	24307	0
T6	503695	14356	0
T7	37224	1067	0
T8	122498	1455	0
T34	528308	219705	0
T35	1239	0	0
T36	147780	30242	0
T37	269630	9312	0
T38	0	7469	0

StMessageFeed_C

Name	Attempts	Matches	Incomplete
Total	1417913732	948984646	0
T1	573346	164562	0
T2	74713	64596	0
T3	335571	259784	0
T6	503695	273175	0
T7	37224	8965	0
T8	122498	75284	0
T34	528308	263460	0
T35	1239	0	0
T36	147780	744812	0
T37	269630	74754	0
T38	0	379497	0

StPadSendMsg_C

Name	Attempts	Matches	Incomplete
Total	1417913732	1993674	0
T1	573346	1687	0
T2	74713	160	0
T3	335571	1065	0
T6	503695	1527	0
T7	37224	93	0
T8	122498	122	0
T34	528308	23552	0
T35	1239	0	0
T36	147780	1884	0
T37	269630	925	0
T38	0	818	0

StPad_C

Name	Attempts	Matches	Incomplete
Total	1417913732	186664	0
T1	573346	182	0
T2	74713	10	0
T3	335571	222	0
T6	503695	140	0
T7	37224	10	0
T8	122498	14	0
T34	528308	2217	0
T35	1239	0	0
T36	147780	289	0
T37	269630	93	0
T38	0	72	0

Line Coverage for Instance : tb.dut.u_sha3.u_pad

	Line No.	Total	Covered	Percent
TOTAL		170	169	99.41
ALWAYS	157	6	6	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
ALWAYS	267	6	6	100.00
ALWAYS	279	3	3	100.00
CONT_ASSIGN	286	1	1	100.00
ALWAYS	293	3	3	100.00
ALWAYS	298	76	75	98.68
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
ALWAYS	558	4	4	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	588	1	1	100.00
ALWAYS	591	5	5	100.00
ALWAYS	603	5	5	100.00
ALWAYS	615	5	5	100.00
ALWAYS	664	10	10	100.00
ALWAYS	680	17	17	100.00
ALWAYS	779	6	6	100.00
ALWAYS	788	6	6	100.00
ALWAYS	798	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
209	1	1
213	1	1
236	1	1
242	1	1
247	1	1
257	1	1
267	1	1
268	1	1
269	1	1
270	1	1
271	1	1
272	1	1
			MISSING_ELSE
279	3	3
286	1	1
293	2	2
294	1	1
298	1	1
301	1	1
302	1	1
304	1	1
306	1	1
307	1	1
309	1	1
310	1	1
312	1	1
314	1	1
316	1	1
325	1	1
327	1	1
328	1	1
330	1	1
333	1	1
345	1	1
347	1	1
348	1	1
350	1	1
351	1	1
352	1	1
354	1	1
356	1	1
361	1	1
363	1	1
364	1	1
366	1	1
375	1	1
377	1	1
378	1	1
380	1	1
381	1	1
383	1	1
385	1	1
386	1	1
387	1	1
388	1	1
389	1	1
392	1	1
394	1	1
400	1	1
402	1	1
403	1	1
405	1	1
414	1	1
416	1	1
418	1	1
421	1	1
424	1	1
425	1	1
426	1	1
427	1	1
428	1	1
430	0	1
435	1	1
437	1	1
438	1	1
447	1	1
451	1	1
452	1	1
454	1	1
455	1	1
456	1	1
458	1	1
460	1	1
466	1	1
467	1	1
469	1	1
470	1	1
472	1	1
474	1	1
480	1	1
481	1	1
494	1	1
495	1	1
			MISSING_ELSE
509	1	1
520	1	1
538	1	1
558	1	1
559	1	1
560	1	1
561	1	1
578	1	1
588	1	1
591	1	1
592	1	1
593	1	1
594	1	1
595	1	1
603	1	1
604	1	1
605	1	1
606	1	1
607	1	1
615	1	1
616	1	1
617	1	1
618	1	1
619	1	1
664	1	1
665	1	1
666	1	1
667	1	1
668	1	1
669	1	1
671	1	1
672	1	1
673	1	1
674	1	1
			MISSING_ELSE
680	1	1
682	1	1
683	1	1
686	1	1
687	1	1
690	1	1
691	1	1
694	1	1
695	1	1
698	1	1
699	1	1
702	1	1
703	1	1
706	1	1
707	1	1
710	1	1
711	1	1
779	1	1
780	1	1
781	1	1
782	1	1
783	1	1
784	1	1
			MISSING_ELSE
788	1	1
789	1	1
790	1	1
791	1	1
792	1	1
793	1	1
			MISSING_ELSE
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sha3.u_pad

	Total	Covered	Percent
Conditions	43	38	88.37
Logical	43	38	88.37
Non-Logical	0	0
Event	0	0

 LINE       209
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION ((mode_i == CShake) ? 1'b1 : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       236
 SUB-EXPRESSION (mode_i == CShake)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       242
 EXPRESSION ((sent_message == block_addr_limit) ? 1'b1 : 1'b0)
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       242
 SUB-EXPRESSION (sent_message == block_addr_limit)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       247
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       257
 EXPRESSION ((&msg_strb_i) != 1'b1)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION (((sent_message + 1'b1) == block_addr_limit) ? 1'b1 : 1'b0)
             ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 SUB-EXPRESSION ((sent_message + 1'b1) == block_addr_limit)
                ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       377
 EXPRESSION (msg_valid_i && msg_partial)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       388
 EXPRESSION (process_latched || process_i)
             -------1-------    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6

 LINE       418
 EXPRESSION (keccak_ack && end_of_block)
             -----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       588
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       604
 EXPRESSION (msg_valid_i & ((~hold_msg)) & ((~en_msgbuf)))
             -----1-----   ------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T62,T43
1	1	0	Covered	T1,T3,T6
1	1	1	Covered	T1,T2,T3

 LINE       616
 EXPRESSION (en_msgbuf | (keccak_ready_i & ((~hold_msg))))
             ----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       616
 SUB-EXPRESSION (keccak_ready_i & ((~hold_msg)))
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sha3.u_pad

Summary for FSM :: st

	Total	Covered	Percent
States	10	10	100.00	(Not included in score)
Transitions	18	16	88.89
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StMessage	330	Covered	T1,T2,T3
StMessageWait	383	Covered	T1,T2,T3
StPad	389	Covered	T1,T2,T3
StPad01	427	Covered	T1,T2,T3
StPadFlush	435	Covered	T1,T2,T3
StPadIdle	333	Covered	T1,T2,T3
StPadRun	421	Covered	T1,T3,T6
StPrefix	328	Covered	T1,T2,T6
StPrefixWait	348	Covered	T1,T2,T6
StTerminalError	495	Covered	T12,T13,T14

transitions	Line No.	Covered	Tests	Exclude Annotation
StMessage->StMessageWait	383	Covered	T1,T2,T3
StMessage->StPad	389	Covered	T1,T2,T3
StMessage->StTerminalError	495	Covered	T12,T14,T32
StMessageWait->StMessage	403	Covered	T1,T2,T3
StMessageWait->StTerminalError	495	Covered	T27,T55,T63
StPad->StPad01	427	Covered	T1,T2,T3
StPad->StPadRun	421	Covered	T1,T3,T6
StPad->StTerminalError	495	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPad01->StPadFlush	452	Covered	T1,T2,T3
StPad01->StTerminalError	495	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPadFlush->StPadIdle	470	Covered	T1,T2,T3
StPadFlush->StTerminalError	495	Not Covered
StPadIdle->StMessage	330	Covered	T1,T3,T6
StPadIdle->StPrefix	328	Covered	T1,T2,T6
StPadIdle->StTerminalError	495	Covered	T13,T46,T47
StPadRun->StPadFlush	435	Covered	T1,T3,T6
StPadRun->StTerminalError	495	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPrefix->StPrefixWait	348	Covered	T1,T2,T6
StPrefix->StTerminalError	495	Not Covered
StPrefixWait->StMessage	364	Covered	T1,T2,T6
StPrefixWait->StTerminalError	495	Covered	T54,T59,T56

---

Branch Coverage for Instance : tb.dut.u_sha3.u_pad

	Line No.	Total	Covered	Percent
Branches		93	89	95.70
TERNARY	213	2	2	100.00
TERNARY	236	2	2	100.00
TERNARY	242	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	588	2	2	100.00
CASE	157	6	5	83.33
IF	267	4	4	100.00
IF	279	2	2	100.00
IF	293	2	2	100.00
CASE	316	23	22	95.65
IF	494	2	2	100.00
CASE	558	4	3	75.00
CASE	591	5	5	100.00
CASE	603	5	5	100.00
CASE	615	5	5	100.00
IF	664	4	4	100.00
IF	779	4	4	100.00
IF	788	4	4	100.00
IF	798	4	4	100.00
CASE	680	9	8	88.89

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	213	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	236	((mode_i == CShake)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	242	((sent_message == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(((sent_message + 1'b1) == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	588	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	157	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T1,T2,T3
L224	Covered	T1,T6,T38
L256	Covered	T1,T2,T3
L384	Covered	T2,T6,T36
L512	Covered	T1,T3,T38
default	Not Covered

	LineNo.	Expression
-1-:	267	if ((!rst_ni))
-2-:	269	if (process_i)
-3-:	271	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	279	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	293	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	316	case (st)
-2-:	325	if (start_i)
-3-:	327	if (mode_eq_cshake)
-4-:	347	if (sent_blocksize)
-5-:	363	if (keccak_complete_i)
-6-:	377	if ((msg_valid_i && msg_partial))
-7-:	381	if (sent_blocksize)
-8-:	388	if ((process_latched || process_i))
-9-:	402	if (keccak_complete_i)
-10-:	418	if ((keccak_ack && end_of_block))
-11-:	426	if (keccak_ack)
-12-:	451	if (sent_blocksize)
-13-:	469	if (keccak_complete_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StPadIdle	1	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
StPadIdle	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T6
StPadIdle	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrefix	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
StPrefix	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
StPrefixWait	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
StPrefixWait	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
StMessage	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T3,T6
StMessage	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T1,T2,T3
StMessage	-	-	-	-	0	0	1	-	-	-	-	-	Covered	T1,T2,T3
StMessage	-	-	-	-	0	0	0	-	-	-	-	-	Covered	T1,T2,T3
StMessageWait	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T3
StMessageWait	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
StPad	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T3,T6
StPad	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T2,T3
StPad	-	-	-	-	-	-	-	-	0	0	-	-	Not Covered
StPadRun	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T6
StPad01	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
StPad01	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T3
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T30,T31,T33

	LineNo.	Expression
-1-:	494	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	558	case (mode_i)

Branches:

-1-	Status	Tests
Sha3	Covered	T1,T2,T3
Shake	Covered	T1,T2,T6
CShake	Covered	T1,T2,T6
default	Not Covered

	LineNo.	Expression
-1-:	591	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T1,T2,T3
MuxPrefix	Covered	T1,T2,T6
MuxFuncPad	Covered	T1,T2,T3
MuxZeroEnd	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	603	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T1,T2,T3
MuxPrefix	Covered	T1,T2,T6
MuxFuncPad	Covered	T1,T2,T3
MuxZeroEnd	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	615	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T1,T2,T3
MuxPrefix	Covered	T1,T2,T6
MuxFuncPad	Covered	T1,T2,T3
MuxZeroEnd	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	664	if ((!rst_ni))
-2-:	667	if (en_msgbuf)
-3-:	672	if (clr_msgbuf)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T6
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	779	if ((!rst_ni))
-2-:	781	if (start_i)
-3-:	783	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	788	if ((!rst_ni))
-2-:	790	if (start_i)
-3-:	792	if (process_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	798	if ((!rst_ni))
-2-:	800	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_o))
-3-:	802	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	680	case (msg_strb)

Branches:

-1-	Status	Tests
7'b0000000	Covered	T1,T2,T3
7'b0000001	Covered	T1,T3,T6
7'b0000011	Covered	T1,T3,T6
7'b0000111	Covered	T1,T3,T6
7'b0001111	Covered	T1,T3,T6
7'b0011111	Covered	T1,T3,T6
7'b0111111	Covered	T1,T3,T6
7'b1111111	Covered	T1,T3,T6
default	Not Covered

---

Assert Coverage for Instance : tb.dut.u_sha3.u_pad

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	4	4	100.00	4	100.00
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AbsorbedPulse_A	1417913732	194067	0	0
AlwaysPartialMsgBuf_M	1417913732	129191	0	0
CompleteBlockWhenProcess_A	1417913732	185637	0	0
DoneCondition_M	1417913732	194060	0	0
DonePulse_A	1417913732	194060	0	0
KeccakAddrInRange_A	1417913732	34458813	0	0
KeccakRunPulse_A	1417913732	2091077	0	0
MessageCondition_M	1417913732	31719870	0	0
ModeStableDuringOp_M	1417913732	33355	0	0
MsgReadyCondition_A	1417913732	946929753	0	0
MsgWidthidth_A	933	933	0	0
NoPartialMsgFifo_M	1417913732	31590679	0	0
Pad01NotAttheEndOfBlock_A	1417913732	186664	0	0
PartialEndOfMsg_M	1417913732	129191	0	0
PrefixLessThanBlock_A	933	933	0	0
ProcessCondition_M	1417913732	194071	0	0
ProcessPulse_A	1417913732	194071	0	0
StartCondition_M	1417913732	194113	0	0
StartProcessDoneMutex_a	1417913732	1417746344	0	0
StartPulse_A	1417913732	194113	0	0
StrengthStableDuringOp_M	1417913732	39514	0	0
u_state_regs_A	1417913732	1417746344	0	0

AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	194067	0	0
T1	573346	192	0	0
T2	74713	10	0	0
T3	335571	246	0	0
T6	503695	148	0	0
T7	37224	11	0	0
T8	122498	15	0	0
T34	528308	2265	0	0
T35	1239	0	0	0
T36	147780	310	0	0
T37	269630	96	0	0
T38	0	77	0	0

AlwaysPartialMsgBuf_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	129191	0	0
T1	573346	175	0	0
T2	74713	0	0	0
T3	335571	214	0	0
T6	503695	131	0	0
T7	37224	10	0	0
T8	122498	13	0	0
T20	0	21	0	0
T34	528308	890	0	0
T35	1239	0	0	0
T36	147780	270	0	0
T37	269630	79	0	0
T38	0	67	0	0

CompleteBlockWhenProcess_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	185637	0	0
T1	573346	181	0	0
T2	74713	10	0	0
T3	335571	219	0	0
T6	503695	139	0	0
T7	37224	10	0	0
T8	122498	14	0	0
T34	528308	2211	0	0
T35	1239	0	0	0
T36	147780	287	0	0
T37	269630	92	0	0
T38	0	72	0	0

DoneCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	194060	0	0
T1	573346	192	0	0
T2	74713	10	0	0
T3	335571	246	0	0
T6	503695	148	0	0
T7	37224	11	0	0
T8	122498	15	0	0
T34	528308	2265	0	0
T35	1239	0	0	0
T36	147780	310	0	0
T37	269630	96	0	0
T38	0	77	0	0

DonePulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	194060	0	0
T1	573346	192	0	0
T2	74713	10	0	0
T3	335571	246	0	0
T6	503695	148	0	0
T7	37224	11	0	0
T8	122498	15	0	0
T34	528308	2265	0	0
T35	1239	0	0	0
T36	147780	310	0	0
T37	269630	96	0	0
T38	0	77	0	0

KeccakAddrInRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	34458813	0	0
T1	573346	19395	0	0
T2	74713	510	0	0
T3	335571	48843	0	0
T6	503695	12304	0	0
T7	37224	950	0	0
T8	122498	1394	0	0
T34	528308	220643	0	0
T35	1239	0	0	0
T36	147780	71006	0	0
T37	269630	9578	0	0
T38	0	52519	0	0

KeccakRunPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	2091077	0	0
T1	573346	1041	0	0
T2	74713	30	0	0
T3	335571	5427	0	0
T6	503695	661	0	0
T7	37224	50	0	0
T8	122498	78	0	0
T34	528308	12979	0	0
T35	1239	0	0	0
T36	147780	5462	0	0
T37	269630	506	0	0
T38	0	2836	0	0

MessageCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	31719870	0	0
T1	573346	15085	0	0
T2	74713	170	0	0
T3	335571	47746	0	0
T6	503695	8673	0	0
T7	37224	759	0	0
T8	122498	1075	0	0
T34	528308	195716	0	0
T35	1239	0	0	0
T36	147780	69082	0	0
T37	269630	7286	0	0
T38	0	50644	0	0

ModeStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	33355	0	0
T1	573346	76	0	0
T2	74713	16	0	0
T3	335571	0	0	0
T6	503695	132	0	0
T7	37224	8	0	0
T8	122498	19	0	0
T20	0	33	0	0
T34	528308	1	0	0
T35	1239	0	0	0
T36	147780	0	0	0
T37	269630	43	0	0
T38	0	31	0	0
T42	0	8	0	0

MsgReadyCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	946929753	0	0
T1	573346	163659	0	0
T2	74713	64576	0	0
T3	335571	259242	0	0
T6	503695	272625	0	0
T7	37224	8920	0	0
T8	122498	75217	0	0
T34	528308	262162	0	0
T35	1239	0	0	0
T36	147780	739350	0	0
T37	269630	74318	0	0
T38	0	379219	0	0

MsgWidthidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	933	933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0

NoPartialMsgFifo_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	31590679	0	0
T1	573346	14910	0	0
T2	74713	170	0	0
T3	335571	47532	0	0
T6	503695	8542	0	0
T7	37224	749	0	0
T8	122498	1062	0	0
T34	528308	194826	0	0
T35	1239	0	0	0
T36	147780	68812	0	0
T37	269630	7207	0	0
T38	0	50577	0	0

Pad01NotAttheEndOfBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	186664	0	0
T1	573346	182	0	0
T2	74713	10	0	0
T3	335571	222	0	0
T6	503695	140	0	0
T7	37224	10	0	0
T8	122498	14	0	0
T34	528308	2217	0	0
T35	1239	0	0	0
T36	147780	289	0	0
T37	269630	93	0	0
T38	0	72	0	0

PartialEndOfMsg_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	129191	0	0
T1	573346	175	0	0
T2	74713	0	0	0
T3	335571	214	0	0
T6	503695	131	0	0
T7	37224	10	0	0
T8	122498	13	0	0
T20	0	21	0	0
T34	528308	890	0	0
T35	1239	0	0	0
T36	147780	270	0	0
T37	269630	79	0	0
T38	0	67	0	0

PrefixLessThanBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	933	933	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0

ProcessCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	194071	0	0
T1	573346	192	0	0
T2	74713	10	0	0
T3	335571	246	0	0
T6	503695	148	0	0
T7	37224	11	0	0
T8	122498	15	0	0
T34	528308	2265	0	0
T35	1239	0	0	0
T36	147780	310	0	0
T37	269630	96	0	0
T38	0	77	0	0

ProcessPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	194071	0	0
T1	573346	192	0	0
T2	74713	10	0	0
T3	335571	246	0	0
T6	503695	148	0	0
T7	37224	11	0	0
T8	122498	15	0	0
T34	528308	2265	0	0
T35	1239	0	0	0
T36	147780	310	0	0
T37	269630	96	0	0
T38	0	77	0	0

StartCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	194113	0	0
T1	573346	192	0	0
T2	74713	10	0	0
T3	335571	246	0	0
T6	503695	148	0	0
T7	37224	11	0	0
T8	122498	15	0	0
T34	528308	2265	0	0
T35	1239	0	0	0
T36	147780	310	0	0
T37	269630	96	0	0
T38	0	77	0	0

StartProcessDoneMutex_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	1417746344	0	0
T1	573346	573294	0	0
T2	74713	74627	0	0
T3	335571	335566	0	0
T6	503695	503279	0	0
T7	37224	37147	0	0
T8	122498	122398	0	0
T34	528308	528298	0	0
T35	1239	1143	0	0
T36	147780	147772	0	0
T37	269630	269577	0	0

StartPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	194113	0	0
T1	573346	192	0	0
T2	74713	10	0	0
T3	335571	246	0	0
T6	503695	148	0	0
T7	37224	11	0	0
T8	122498	15	0	0
T34	528308	2265	0	0
T35	1239	0	0	0
T36	147780	310	0	0
T37	269630	96	0	0
T38	0	77	0	0

StrengthStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	39514	0	0
T1	573346	88	0	0
T2	74713	21	0	0
T3	335571	2	0	0
T6	503695	136	0	0
T7	37224	7	0	0
T8	122498	24	0	0
T34	528308	2	0	0
T35	1239	1	0	0
T36	147780	2	0	0
T37	269630	55	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	1417746344	0	0
T1	573346	573294	0	0
T2	74713	74627	0	0
T3	335571	335566	0	0
T6	503695	503279	0	0
T7	37224	37147	0	0
T8	122498	122398	0	0
T34	528308	528298	0	0
T35	1239	1143	0	0
T36	147780	147772	0	0
T37	269630	269577	0	0

---

Cover Directives for Properties: Details

Name	Attempts	Matches	Incomplete
StComplete_C	1417913732	18847821	0
StMessageFeed_C	1417913732	948984646	0
StPadSendMsg_C	1417913732	1993674	0
StPad_C	1417913732	186664	0

StComplete_C

Name	Attempts	Matches	Incomplete
Total	1417913732	18847821	0
T1	573346	18624	0
T2	74713	970	0
T3	335571	24307	0
T6	503695	14356	0
T7	37224	1067	0
T8	122498	1455	0
T34	528308	219705	0
T35	1239	0	0
T36	147780	30242	0
T37	269630	9312	0
T38	0	7469	0

StMessageFeed_C

Name	Attempts	Matches	Incomplete
Total	1417913732	948984646	0
T1	573346	164562	0
T2	74713	64596	0
T3	335571	259784	0
T6	503695	273175	0
T7	37224	8965	0
T8	122498	75284	0
T34	528308	263460	0
T35	1239	0	0
T36	147780	744812	0
T37	269630	74754	0
T38	0	379497	0

StPadSendMsg_C

Name	Attempts	Matches	Incomplete
Total	1417913732	1993674	0
T1	573346	1687	0
T2	74713	160	0
T3	335571	1065	0
T6	503695	1527	0
T7	37224	93	0
T8	122498	122	0
T34	528308	23552	0
T35	1239	0	0
T36	147780	1884	0
T37	269630	925	0
T38	0	818	0

StPad_C

Name	Attempts	Matches	Incomplete
Total	1417913732	186664	0
T1	573346	182	0
T2	74713	10	0
T3	335571	222	0
T6	503695	140	0
T7	37224	10	0
T8	122498	14	0
T34	528308	2217	0
T35	1239	0	0
T36	147780	289	0
T37	269630	93	0
T38	0	72	0